• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of Biomedical Engineering Research
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• v.28 no.2
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• pp.205-211
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• 2007

A novel envelope extraction algorithm for speech processor of cochlear implants, called adaptation algorithm, was developed which is based on a adaptation effect of the inner hair cell(IHC)/auditory nerve(AN) synapse. We achieved acoustic simulation and hearing experiments with 12 normal hearing persons to compare this adaptation algorithm with existent standard envelope extraction method. The results shows that speech processing strategy using adaptation algorithm showed significant improvements in speech recognition rate under most channel/noise condition, compared to conventional strategy We verified that the proposed adaptation algorithm may yield better speech perception under considerable amount of noise, compared to the conventional speech processing strategy.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• Proceedings of the KOSOMBE Conference
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• v.1991 no.05
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• pp.89-93
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• 1991

The purpose of this reserch is to design the blood cell counting instrument which can measure the number of RBC(Red Blood Cell) and WBC(White Blood Cell) including many other blood component. The proposed method uses the electrical impedence method and the new discrimination method wi th DSP chip and software algorithm. The system consist of control unit, blood cell discrimination unit, hemoglobin spectrometer, post detect ion processor unit, and IBM-PC interface unit. In this paper, the discrimination system has been implemented using digital signal processor, which result in the reduction of system hardware and cost. The system is helpful in providing necessary clinical test for screen test and quality control of hematology.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.8 s.251
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• pp.731-740
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• 2006

The solid oxide fuel cell (SOFC) is expected to be a candidate for distributed power sources in the next generation, due to its high efficiency and high-temperature waste heat utilization. In this study, the 5-cell SOFC stack was operated with pure hydrogen or reformed gas at anode side and air at cathode side. When stack was operated with diesel and methane ATR reformer, the influence of the $H_2O/C,\;O_2/C$ and GHSV on performance of stacks have been investigated. The result shows that the cell voltage was decreased with the increase of $H_2O/C$ and $O_2/C$ due to the partial pressure of fuel and water, and cell voltage was more sensitive to $O_2/C$ than $H_2O/C$. Next, the dynamic model of SOFC system included with ATR reformer was established and compared with experimental data. Based on dynamic model, the operation strategy to optimize SOFC-Reformer system was suggested and simulated.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• Proceedings of the Korea Crystallographic Association Conference
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• 2003.11a
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• pp.7-7
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• 2003

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.