• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.669-670
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• 2006

This paper describes the functions and design technology of the T-DMB (Terrestrial Digital Multimedia Broadcasting) receiver. T-DMB is a novel broadcasting media that can provide high-quality video and audio services. In this paper, we will describe the VLSI implementation of RF, Baseband and Multimedia Chip for T-DMB Receiver. The designed DMB SoC has low power consumption and has been implemented using a standard-cell library in 0.18um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.718-727
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• 2014

In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

• 한국전산유체공학회:학술대회논문집
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• 1999.05a
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• pp.35-47
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• 1999

The development of a parallelized aerodynamic simulation process involving moving bodies is presented. The implementation of this process is demonstrated using a fully systemized Chimera methodology for steady and unsteady problems. This methodology consist of a Chimera hole-cutting, a new cut-paste algorithm for optimal mesh. interface generation and a two-step search method for donor cell identification. It is fully automated and requires minimal user input. All procedures of the Chimera technique are parallelized on the Cray T3E using the MPI library. Two and three-dimensional examples are chosen to demonstate the effectiveness and parallel performance of this procedure.

• The Korean Journal of Zoology
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• v.37 no.1
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• pp.12-18
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• 1994

The prothoracicotropic hormone (PTTH) produced by the neurosecretory cells in insects is involved in molting and metamorphosis by activating the prothoracic frins) glands to secrete ecdysone (or related ecdvsteroidsl. In the present study, the small PTTH-like gene was isolated by screening of CDNA library using the bombvxin (corresponding to small PTTH in Bombvx moril gene probe in Drosophilo melonogaster. It showed 50-6096 sequence homology to bombyxin gene. The expression patterns of this gene showed developmental stage- and tissue-dependent manners. The mRNA was detected only in the late third instar larval-prepupa which is stases showing the highest hormonal activity to secrete ecdysteroids, and detected in the brain pan of the Isle third instar lanrae.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• The Korean Journal of Zoology
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• v.38 no.1
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• pp.49-54
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• 1995

본 연구자들은 근원세포를 면역시켜 얻은 hybidoma들을 검색하여. 계배 근원세포의 분화와 관련된 단백질을 인지하여 분화를 억제하는 대과가 있는 monoclonal antibody 3H35를 선별하여 그 항원을 확인한 바 있다(Kim et af.. (1992), Korean J. Zool 35 29-36) 본 연구에서는 λZAP에 cloning된 chicken muscle CDNA library들을 lacZ fusion protein으로 발현시켜 항체 3H35로 검색하여 그 유전자를 찾아내었다. 선별한 CDNA clone 중 C59의 삽입 절편은 1.6 kb이었고, 발현시킨 facE fusion protein 은 60 kDa로, f-galactosidase에 대한 항체에 반응하며 3H35와도 반응함을 immunoaffinitv adsorbant와 immunoblot으로 확인하였다 Clone C59의 삽입 절편의 염기서열을 분석한 결과, 실제 유전자는 1.6 kb 이상이며, 알려진 어느 다른 유전자와도 관련이 없는 새로운 근특이 유전자로 판단되었다. 아미노산으로 전환시켰을 때 31개의 특이한 서열이 7차례 반복된 부분이 나타났으며 이 서열의 23개가 일정하게 보존되어있고 나머지 서열의 아미노산의 polarity도 매우 유사하게 효존되어있다. 이들의 보존성이 극히 높은 것으로 보아 독특한 기능을 수행하는 domain으로 추정된다.

• Journal of Life Science
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• v.17 no.6 s.86
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• pp.841-846
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• 2007

The identification of tumor antigens is essential for the development of anticancer therapeutic vaccines and clinical diagnosis of cancer. SEREX (serological analysis of recombinant cDNA expression library)has been used to identify such tumor antigens by screening sera of cancer patients with cDNA ex-pression libraries. SEREX-defined antigens provide markers for the diagnosis of cancers. SEREX is also a powerful method for the development of anticancer therapeutics. The development of anticancer vaccines requires that tumor antigens can elicit antigen-specific antibodies or T lymphocytes. This re-view provides information on the application of SEREX for discovery of tumor antigens.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.8
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• pp.406-413
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• 2001

본 논문은 CMOS 디지털 회로에서 글리치(glitch)에 의해 발생하는 전력소모를 줄이기 위한 효율적인 휴리스틱 알고리즘을 제시한다. 제안된 알고리즘은 사이징되는 게이트의 위치와 양에 따라 게이트 사이징을 세 가지 type으로 분류한다. 또한 버퍼삽입은 삽입되는 버퍼의 위치에 따라서 두 가지 type으로 분류한다. 글리치 제거 효과를 극대화하기 위해서 비용과 이득의 상관관계를 고려하여 하나의 최적화 과정 안에서 세 가지 type의 게이트 사이징과 두 가지 type의 버퍼삽입을 혼합한다. 제안된 알고리즘은 0.5$\mu\textrm{m}$ 표준 셀 라이브러리(standard cell library)를 이용한 LGSynth91 벤치마크 회로에 대한 테스트 결과 효율성을 검증하였다. 실험결과는 평균적으로 69.98%의 글리치 감소와 28.69%의 전력감소를 얻을 수 있었으며 이것은 독립적으로 적용된 게이트 사이징과 버퍼 삽입 알고리즘에 의한 것 보다 좋은 결과이다.