• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• ETRI Journal
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• v.24 no.5
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• pp.391-397
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• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.15-24
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• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Journal of Microbiology and Biotechnology
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• v.16 no.9
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• pp.1468-1471
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• 2006

The last step in L-carnitine biosynthesis in eukaryotic organisms is mediated by ${\gamma}$-butyrobetaine hydroxylase (EC1.14.11.1), a dioxygenase that converts ${\gamma}$-butyrobetaine to L-carnitine. This enzyme was previously identified from rat liver and humans, and the peptide sequence of human ${\gamma}$-butyrobetaine hydroxylase was used to search the Neurospora crassa genome database, which led to an identification of an open reading frame (ORF) consisting of 1,407 bp encoding a polypeptide of 468 amino acids. When this protein was expressed in Saccharomyces cerevisiae, the crude cell-free extract exhibited ${\gamma}$-butyrobetaine hydroxylase activity.

• Environmental Analysis Health and Toxicology
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• v.18 no.4
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• pp.287-294
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• 2003

출아형 효모 Saccharomyces cerevisiae RAD3 유전자는 절제회복 및 세포의 생존에 필수적이며, DNA dependent ATPase와 DNA-RNA helicase활성을 가지고 있는 것으로 알려져 있다. 본 연구는 분열형 효모 Schizosaccharomyces pombe에서 절제회복과 세포의 생존에 필수적인 출아형 효모 RADS유전자와 유사한 유전자를 S. pombe genomic DNA library에서 분리하여 그 특성을 연구하였다. 분리한 RADS 유사유전자를 HRD3 유전자라 명명하였다. 발현 vector pET3a를 이용하여 분리한 HRD3 유전자를 과 발현하였을 때 HRD3단백질은 숙주단백질의 합성 억제 또는 분해 촉진을 유발하여 숙주세포인 대장균에 독성 효과를 나타냄이 관찰되었다. HRD3유전자와 lacZ유전자를 융합시킨 여러 가지 재조합 vector를 만들어 이들 융합단백질을 분리하였다. 이 결과 HRD3단백질의 카르복실 말단 부위가 DNA회복기능과 대장균에서의 독성효과를 나타내는 중요한 부위로 생각된다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.