• Title/Summary/Keyword: carrier recovery

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A New Decision-Directed Carrier Recovery Algorithm (새로운 결정지향 반송파 복원 알고리즘)

  • 고성찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.1028-1035
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    • 1999
  • To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

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An FPGA Design of High-Speed QPSK Demodulator (고속 무선 전송을 위한 QPSK 복조기 FPGA 설계)

  • 정지원
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.12
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    • pp.1248-1255
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    • 2003
  • High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6[Mbps]. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode

  • Bouangeune, Daoheung;Choi, Sang-Sik;Cho, Deok-Ho;Shim, Kyu-Hwan;Chang, Sung-Yong;Leem, See-Jong;Choi, Chel-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.495-502
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    • 2014
  • Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

Software Design Methodology of OFDM DVB-T Receiver using DSP-based Platform (DSP 기반 플랫폼을 이용한 OFDM DVB-T 반송파 복원부의 소프트웨어 설계 방법)

  • 신정헌;유형석;윤주현;박찬섭;정해주;조준동
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.55-59
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    • 2003
  • In this paper, we estimate the performance requirements of general-purpose DSP for Carrier Recovery of OFDM DVB-T receiver. Firstly, we transported the designed fixed-point OFDM DVB-T model to a floating-point software model written in C. Then, we measured the number of instruction cycles required for operation of Carrier Recovery in time. We use SignalMaster$\^$TM/ DSP platform of LYRtech Inc. as a environment of estimation, and Simulink$\^$TM/ as a graphical interface, Code Composer StudioTM of TI as profiler and compiler, and SPW$\^$TM/ for presenting functional reliability and comparing the performance distortion with fixed-point model. As a result, we show the required number of DSPs in our DSP-based system, and introduce the need of Multi-DSP-based system.

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Performance Analysis of Clock Recovery for OFDM/QPSK-DMR System Using Band Limited-Pulse Shaping Filter (대역 제한 필터를 이용하는 OFDM/QPSK-DMR 시스템을 위한 클럭 복조기의 성능 분석)

  • 안준배;양희진;강희곡;오창헌;조성준
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.245-249
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    • 2004
  • In this paper, we have proposed a clock recovery algorithm of Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio(OFDM/QPSK-DMR) system using Band Limited-Pulse Shaping Filter(BL-PSF) and compared the clock phase error variance of OFDM/QPSK-DMR system with that of single carrier DMR system. The OFDM/QPSK-DMR system using windowing method requires training sequence or Cyclic Prefix (CP) to synchronize the clock phase of received signal. But transmit efficient is increased in our proposed DMR system because of no using redundant data such as training sequence or CP. The proposed clock recovery algorithm is simply realized in the OFDM/QPSK-DMR system using BL-PSF. The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DR system under Additive White Gaussian Noise(AWGN) environment.

A Study on the Method to Treat Carrier Frequency Offset for VDES Receiver (VDES 수신기를 위한 주파수 옵셋 처리 방안 연구)

  • Ryu, Hyeong-Jik;Kim, Hye-Jin;Kim, Won-Yong;Park, Gae-Myeong;Kim, Jun-Tae;Yoo, Jin-Ho
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • 2018.11a
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    • pp.310-312
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    • 2018
  • In this paper, We stduy addtional consideration and method to treat carrier frquency offset on defined system parameter & requirements in IALA G1139, previous studied consecutively. We studied the method to treat carrier frequency offset by extending length of training symbol and by differential modulation. This study will publish and argue in IALA ENAV22. We will decide a method to treat carrier frequency offset from result of IALA ENAV22.

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Effect of Amplified Spontaneous Emission on the Gain Recovery of a Semiconductor Optical Amplifier

  • Lee, Hojoon
    • Korean Journal of Optics and Photonics
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    • v.29 no.1
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    • pp.32-39
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    • 2018
  • The impact of the amplified spontaneous emission (ASE) on the gain recovery time of a bulk semiconductor optical amplifier (SOA) is investigated. The gain-recovery time is obtained by determining the time evolution of the gain, carrier density, and ASE in an SOA, after the propagation of a short pump pulse and continuous-wave (CW) probe of gain dynamics. In the simulation, a wide-band-semiconductor model, which can be characterized by the material gain coefficient over a wide wavelength range, is used, because the gain bandwidth of a practical SOA is very wide. The pump pulse and counterpropagating CW probe field are considered in the simulation, with the ASE noise spectrum equally divided.