• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2712-2714
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• 1999

The small signal model for input series-output parallel connected converter system employing charge control together with input capacitor voltage feedback loop is developed. From the model developed, the effect of input capacitor voltage feedback loop to the system stability and outer loop compensator design is analyzed. Theoretical results and simulation show that input capacitor voltage feedback loop has no critical effects on the system stability, so the system can be reduced to a equivalent single module for the stability analysis and outer loop compensator design.

• Journal of Power Electronics
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• v.13 no.6
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• pp.1008-1015
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• 2013

By using fractional calculus and the circuit-averaging technique, the modeling and analysis of a Buck converter with fractional order inductor and fractional order capacitor in discontinuous conduction mode (DCM) operations is investigated in this study. The equivalent averaged circuit model of the fractional order Buck converter in DCM operations is established. DC analysis is conducted by using the derived DC equivalent circuit model. The transfer functions from the input voltage to the output voltage, the duty cycle to the output voltage, the input impedance, and the output impedance of the fractional order Buck converter in DCM operations are derived from the corresponding AC-equivalent circuit model. Results show that the DC equilibrium point, voltage ratio, and all derived transfer functions of the fractional order Buck converter in DCM operations are affected by the inductor order and/or capacitor order. The fractional order inductor and fractional order capacitor are designed, and PSIM simulations are performed to confirm the correctness of the derivations and theoretical analysis.

• Journal of Power Electronics
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• v.19 no.2
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• pp.529-539
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• 2019

The modular multilevel converter (MMC) has become a promising topology for high-voltage direct current (HVDC) transmission systems. To control a MMC system properly, the ac-side current, circulating current and submodule (SM) capacitor voltage are taken into consideration. This paper proposes a low-computation indirect model predictive control (IMPC) strategy that takes advantages of the conventional MPC and has no weighting factors. The cost function and duty cycle are introduced to minimize the tracking error of the ac-side current and to eliminate the circulating current. An optimized merge sort (OMS) algorithm is applied to keep the SM capacitor voltages balanced. The proposed IMPC strategy effectively reduces the controller complexity and computational burden. In this paper, a discrete-time mathematical model of a MMC system is developed and the duty ratio of switching state is designed. In addition, a simulation of an eleven-level MMC system based on MATLAB/Simulink and a five-level experimental setup are built to evaluate the feasibility and performance of the proposed low-computation IMPC strategy.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1659-1669
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• 2018

An improved circulating current suppression control method is proposed in this paper. In the proposed controller, an outer loop of the average capacitor voltage control model is used to balance the sub-module capacitor voltage. Meanwhile, an individual voltage balance controller and an arm voltage balance controller are also used. The DC and harmonic components of the circulating current are separated using a low pass filter. Therefore, a multiple quasi-proportional-resonant (multi-quasi-PR) controller is introduced in the inner loop to eliminate the circulating harmonic current, which mainly contains second-order harmonic but also contains other high-order harmonics. In addition, the parameters of the multi-quasi-PR controller are designed in the discrete domain and an analysis of the stability characteristic is given in this paper. In addition, a simulation model of a three-phase MMC system is built in order to confirm the correctness and superiority of the proposed controller. Finally, experiment results are presented and compared. These results illustrate that the improved control method has good performance in suppressing circulating harmonic current and in balancing the capacitor voltage.

• Journal of Power Electronics
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• v.19 no.4
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• pp.869-880
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• 2019

Due to the inherent feedforward of load current, capacitor current (CC) control shows a fast transient response that makes it suitable for the power supplies used in various portable electronic devices. However, considering the effect of the outer voltage loop, the stable range of the duty-cycle is significantly diminished in CC controlled buck converters. To investigate the stability effect of the outer voltage loop on buck converters, a CC controlled buck converter with a proportion-integral (PI) compensator is taken as an example, and its second-order discrete-time model is established. Based on this model, the instability caused by the duty-cycle is discussed with consideration of the outer voltage loop. Then the dynamical effects of the feedback gain of the PI compensator and the equivalent series resistance (ESR) of the output capacitor on the CC controlled buck converter with a PI compensator are studied. Furthermore, the design-oriented closed-loop stability criterion is derived. Finally, PSIM simulations and experimental results are supplied to verify the theoretical analyses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.38-39
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• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.71-80
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• 2004

A new SSN(Simultaneous Switching Noise) model is presented, which can afford to investigate SSN due to integrated circuit package. It is shown that previous SSN models are not accurate enough to be practical since they do not take decoupling capacitor into account. In this paper, a new SSN model including the decoupling capacitor is developed. It is verified that the model has excellent agreement(within $5\%$ error) with HSPICE simulation which employs TSMC 0.18um CMOS process technology.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.270-275
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• 2019

Mica capacitor is being adopted for high voltage firing unit of guided weapon system because of its superior impact enduring property relative to ceramic capacitor. Reliability of localized mica high voltage capacitors was verified through environmental test like terminal strength test, humidity test, thermal shock test and accelerated life test for application to high voltage firing unit. Failure mode of mica capacitor is a decrease of insulation resistance and its final dielectric breakdown. Main constants of accelerated life model were derived experimentally and voltage constant and activation energy were 5.28 and 0.805 eV respectively. Lifetime of mica capacitor at normal use condition was calculated to be 38.5 years by acceleration factor, 496, and lifetime at accelerated condition and this long lifetime confirmed that mica high voltage capacitor could be applied for firing unit.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.