• Journal of information and communication convergence engineering
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• 제15권1호
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• pp.62-71
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• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.387-400
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• 2017

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

• Journal of Power Electronics
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• 제12권1호
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• pp.172-180
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• 2012

Z-source inverters (ZSI) are used to realize both DC voltage boost and DC-AC inversion in single stage with a reduced number of power switching devices. A traditional MPPT control algorithm provides a shoot-through interval which should be inserted in the switching waveforms of the inverter to output the maximum power to the Z-network. At this instant, the voltage across the Z-source capacitor is equal to the output voltage of a PV array at the maximum power point (MPP). The control of the Z-source capacitor voltage beyond the MPP voltage of a PV array is not facilitated in traditional MPPT algorithms. This paper presents a unified MPPT control algorithm to simultaneously achieve MPPT as well as Z-source capacitor voltage control. Development and implementation of the proposed algorithm and a comparison with traditional results are discussed. The effectiveness of the proposed unified MPPT control strategy is implemented in Matlab/Simulink software and verified by experimental results.

• ETRI Journal
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• 제35권4호
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• pp.594-602
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• 2013

This paper proposes printed organic one-time programmable read-only memory (PROM). The organic PROM cell consists of a capacitor and an organic p-type metal-oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store "0." Some organic PROM cells are programmed to "1" by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16-bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with -50 V, and they are read out with -20 V. The area of the 16-bit organic PROM array is 70.6 $mm^2$.

• 한국통신학회논문지
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• 제9권1호
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• pp.30-38
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• 1984

本論文에서는 中心周波數를 클럭周波數에 의해 線型的으로 변화시킬 수 있고 選揮度와 最大利得은 캐패시터 array에 의해 디지틀信號로 制擧할 수 있는 프로그램 可能한 2次SC filter를 構成하였다. 또한 이 filter를 이용하여 formant音聲合成시스템을 構成하고 韓國誤子音을 合成함으로써 이 filter를 가지고 韓國語의 대부분이 吟聲을 實時間으로 合成할 수 있다는 可能性을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.579-587
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• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• 전기학회논문지
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• 제58권1호
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• pp.137-146
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• 2009

We present a micromechanical digital-to-analog (DA) variable capacitor using a parallel digital actuator array, capable of accomplishing high-Q tuning. The present DA variable capacitor uses a parallel interconnection of digital actuators, thus achieving a low resistive structure. Based on the criteria for capacitance range ($0.348{\sim}1.932$ pF) and the actuation voltage (25 V), the present parallel DA variable capacitor is estimated to have a quality factor 2.0 times higher than the previous serial-parallel DA variable capacitor. In the experimental study, the parallel DA variable capacitor changes the total capacitance from 2.268 to 3.973 pF (0.5 GHz), 2.384 to 4.197 pF (1.0 GHz), and 2.773 to 4.826 pF (2.5 GHz), thus achieving tuning ratios of 75.2%, 76.1%, and 74.0%, respectively. The capacitance precisions are measured to be $6.16{\pm}4.24$ fF (0.5 GHz), $7.42{\pm}5.48$ fF (1.0 GHz), and $9.56{\pm}5.63$ fF (2.5 GHz). The parallel DA variable capacitor shows the total resistance of $2.97{\pm}0.29\;{\Omega}$ (0.5 GHz), $3.01{\pm}0.42\;{\Omega}$ (1.0 GHz), and $4.32{\pm}0.66\;{\Omega}$ (2.5 GHz), resulting in high quality factors which are measured to be $33.7{\pm}7.8$ (0.5 GHz), $18.5{\pm}4.9$ (1.0 GHz), and $4.3{\pm}1.4$ (2.5 GHz) for large capacitance values ($2.268{\sim}4.826$ pF). We experimentally verify the high-Q tuning capability of the present parallel DA variable capacitor, while achieving high-precision capacitance adjustments.

• 한국인터넷방송통신학회논문지
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• 제24권2호
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• pp.139-145
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• 2024

본 논문에서는 VCO 이득(Kvco) 변화가 작은 현대 무선 통신 시스템의 핵심 구성 요소 중 하나인 전압 제어 발진기(VCO)의 설계를 제시하였다. 기존의 큰 Kvco 변화를 보상하기 위해 병렬 커패시터 뱅크 어레이가 있는 기존 LC-탱크에 직렬 배랙터 뱅크가 추가되었다. 또한 넓은 튜닝 범위를 유지하면서 우수한 위상 잡음 성능을 달성하기 위해 혼합 거친/미세 튜닝 방식(직렬 배랙터 어레이 및 병렬 커패시터 어레이)이 선택되었다. 스위치드 배랙터 어레이 뱅크는 추가 디지털 회로 없이 스위치드 커패시터 어레이에 대해 동일한 디지털 코드에 의해 제어됩니다. 1.2V의 낮은 전압에서 사용하기 위해 본 논문에서 제안된 전류 참조 회로는 공통 게이트를 보다 안전하게 제거한 안전성을 위해 전류 참조 회로를 사용하였다. TSMC 0.13 ㎛ CMOS RF 기술로 구현된 제안된 VCO는 9.6% 미만의 Kvco(VCO 이득) 변화로 4.4GHz에서 5.3GHz로 조정할 수 있다. 1.2V 공급에서 3.1mA를 소비하는 동안 VCO는 5.3GHz의 반송파에서 오프셋 1MHz에서 -120dBc/Hz 위상 잡음을 갖을 수 있었다.

• 한국정보통신학회논문지
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• 제20권9호
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• pp.1755-1762
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• 2016

본 논문에서는 입력전압 범위가 향상된 저면적 이중출력 스위치드 커패시터 DC-DC 변환기를 제안하였다. 기존의 스위치드 커패시터는 면적이 작고 저렴하지만, 효율적인 전압변환을 하는 입력전압의 범위가 좁고 다중출력의 경우 면적이 커지고 전력효율이 낮아진다. 제안된 스위치드 커패시터 DC-DC 변환기는 입력전압에 따라 커패시터 어레이 구조를 변경하여 최적의 효율을 갖는 입력 범위를 증가시켰다. 그리고 두 개의 스위치 어레이를 공유함으로써 스위치와 커패시터 수를 32개에서 25개로 줄였다. 제안된 변환기는 $0.18{\mu}m$ CMOS 공정에서 제작하였다. 시뮬레이션 결과 입력전압 범위는 0.7~1.8V이고, 최대 전력 효율은 90%이며, 칩의 면적은 $0.255mm^2$이다.