• Proceedings of the KSME Conference
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• 2001.06d
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• pp.654-659
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• 2001

A new non-contact method of the frost thickness measurement has been developed. The method is based on the digital image processing technique to identify the reflection edge of the image captured by a CCD camera under laser sheet light illumination. To insure the accuracy of frost layer thickness, an in-situ calibration procedure is carried out with a calibration target with 0.5mm holes. Using the mapping function obtained by the calibration procedure, the contour of frost surface can be estimated with sub-pixel resolutions. The developed method is applied to study the effect of cooling plate temperature on the frost thickness in a small low speed wind tunnel.

• ETRI Journal
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• v.35 no.4
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• pp.718-721
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• 2013

This letter proposes a novel calibration method for a multiport amplifier (MPA) to achieve optimum port-to-port isolation by correcting both the amplitude and phase of the calibration signals. The proposed architecture allows for the detection of the phase error and amplitude error in each RF signal path simultaneously and can enhance the calibrated resolution by controlling the analog phase shifters and attenuators. The designed $2{\times}2$ and $4{\times}4$ MPAs show isolation characteristics of 30 dB and 27 dB over a frequency range of 19.5 GHz to 22.5 GHz, respectively.

• ETRI Journal
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• v.44 no.5
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• pp.816-825
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• 2022

Nondestructive testing, which can monitor a product's interior without disassembly, is becoming increasingly essential for industrial inspection. Computed laminography (CL) is widely used in this application, as it can reconstruct a product, such as a printed circuit board, into a three-dimensional (3D) high-magnification image using X-rays. However, such high-magnification scanning environments can be affected by minute vibrations of the CL device, which can generate motion artifacts in the 3D reconstructed image. Since such vibrations are irregular, geometric corrections must be performed at every scan. In this paper, we propose a geometry calibration method that can correct the geometric information of CL scans based on the image without using geometry calibration phantoms. The proposed method compares the projection and digitally reconstructed radiography images to measure the geometric error. To validate the proposed method, we used both numerical phantom images at various magnifications and images obtained from real industrial CL equipment. The experiment results confirmed that sharpness and contrast-to-noise ratio (CNR) were improved.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.764-766
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• 1998

An evaluation method for oxygen permeable characteristics of the membrane covering to each cathode of multiple cathode - single anode type dissolved oxygen sensor, which has high reproducibility and is capable of measuring multiple components in solutions. For this purpose, a measuring circuit for the multiple cathode type DO sensor was designed to lower the noise signal by adapting a digital LPF to readout the sensor output accurately. Digital LPF is designed by setting up the transfer function to set the cutoff frequency to 10Hz, and the transfer function is programmed by C language, and then the filtering characteristics are evaluated with the simulation and experiments. Using this LPF added measuring circuit for the multiple cathode type DO sensor, we have obtained the calibration factor for each cathode to calibrate the variation of the output signals. The calibration factor was obtained by measuring the sensor output signal followed by oxygen partial pressure, using the same oxygen permeable membrane at each cathode of the multiple cathode type DO sensor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Smart Media Journal
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• v.2 no.1
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• pp.27-30
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• 2013

In this paper, we research the hand tracking and calibration algorithm using the EPIC sensor. We analyze the characteristics of EPIC sensor to be more sensitive in the around E-filed, and then we implement the 2-dimensional axis-transformation using the difference of detected amplitude between EPIC sensors. In addition, we implement the calibration algorithm considering the characteristics of EPIC sensor, and then we apply the Kalman filter to efficiently track a target. Thus, we implement the environment of window applications for verification and analysis the implemented algorithm. In turn, we use the DAQ API to extract the analog data. The DAQ hardware has the function of measuring and generating an electrical signal. Moreover, we confirm the movement of mouse cursor by detecting the potential difference depending on the movement of the user's hands.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.4
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• pp.61-67
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• 2008

In this papar, the flow meter system for pulverized coal is developed for the pulverizer-burner system of the boiler or the blast furnace. The sensor of the system a lied the capacitance with a pair of electrode on the outer wall of the electric insulator pipe. The circuit is designed for the measurement of the granule flow density combining as a measuring electrode and a reference. In order to measure granule-flow density, the calibration curve between the weight measured from loadcell and the voltage from the circuit is created. It is verified that the flow meter system has reliability and accuracy using on-line test.