• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.89-98
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• 2010

In current digital broadcasting systems, GEM(Globally Executable MHP)-based middlewares such as MHP(Multimedia Home Platform), OCAP(OpenCable Application Platform), ACAP(Advanced Common Application Platform) are the norm. Despite much of the common characteristics shared, such as MPEG-2 and DSM-CC(Digital Storage Media-Command and Control) protocols, the information and data structures they need are slightly different, which results in incompatibility issues. In this paper, in line with an effort to develop an integrated DTV middleware, we propose a general-purpose, reconfigurable DSM-CC architecture for supporting various standard GEM-based middlewares without code modifications. First, we identify DSM-CC components that are common and thus can be shared by all GEM-based middlewares. Next, the system is provided with middleware-specific information and data structures in the form of XML. Since the XML information can be parsed dynamically at run time, it can be interchanged either statically or dynamically for a specific target middleware. As for the performance issues, the response time and usage frequency of DSM-CC module highly contribute to the performance of STB(Set-Top-Box). In this paper, we also propose an efficient application cache management strategy and evaluate its performance. The performance result has shown that the cache strategy reflecting user preferences greatly helps to reduce response time for executing application.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.117-123
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• 2013

In the recent cloud storage environment, the amount of SSD (Solid-State Drive) replacing with the traditional hard disk drive is increasing. Management of SSD for its space efficiency has become important since SSD provides fast IO performance due to no mechanical movement whereas it has wearable characteristics and does not provide in place update. In order to manage space efficiency of SSD, data de-duplication technique is frequently used. However, this technique occurs much overhead because it consists of data chunking, hasing and hash matching operations. In this paper, we propose new data de-duplication method using PRAM cache. The proposed method uses hierarchical hash tables and LRU(Least Recently Used) for data replacement in PRAM. First hash table in DRAM is used to store hash values of data cached in the PRAM and second hash table in PRAM is used to store hash values of data in SSD storage. The method also enhance data reliability against power failure by maintaining backup of first hash table into PRAM. Experimental results show that average writing frequency and operation time of the proposed method are 44.2% and 38.8% less than those of existing data de-depulication method, respectively, when three workloads are used.

• Annual Conference of KIPS
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• 2013.05a
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• pp.41-44
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• 2013

병렬 및 분산 컴퓨팅 영역에서 기존 실험의 대부분은 속도 개선만을 고려하여 알고리즘을 설계 하였다. 이 연구는 일정 수준의 속도 개선을 보이면서도 에너지 절감효과를 기대하고자 저장장치 및 캐쉬의 활용을 생각하여 알고리즘을 설계하는 연구를 진행 한다. 이를 보이기 위해 입출력 비중이 높은 경우를 대표하는 외부 정렬 실험과 순수 연산의 비중이 높은 경우를 대표하는 매트릭스 실험을 하였다. 연구 결과를 통해 저장장치 및 캐쉬를 고려한 알고리즘이 그린 컴퓨팅에 이바지 할 수 있다는 것을 말하고자 한다.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.2
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• pp.134-145
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• 2004

With rapid growth in the amount of data transferred on the Internet, traditional storage systems have reached the limits of their capacity and performance. SAN (Storage Area Network), which connects hosts to disk with the Fibre Channel switches, provides one of the powerful solutions to scale the data storage and servers. In this environment, the maintenance of data consistency among hosts is an important issue because multiple hosts share the files on disks attached to the SAN. To preserve data consistency, each host can execute the disk I/O whenever disk read and write operations are requested. However, frequent disk I/O requests cause the deterioration of the overall performance of a SAN cluster. In this paper, we introduce a SANtopia global buffer manager to improve the performance of a SAN cluster reducing the number of disk I/Os. We describe the design and algorithms of the SANtopia global buffer manager, which provides a buffer cache sharing mechanism among the hosts in the SAN cluster. Micro-benchmark results to measure the performance of block I/O operations show that the global buffer manager achieves speed-up by the factor of 1.8-12.8 compared with the existing method using disk I/O operations. Also, File system micro-benchmark results show that SANtopia file system with the global buffer manager improves performance by the factor of 1.06 in case of directories and 1.14 in case of files compared with the file system without a global buffer manager.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.605-619
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• 2003

The main memory DBMS(MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. In this paper, we discuss the index manager of the Tachyon, a next-generation MMDBMS. Recently, the gap between the CPU processing and main memory access times is becoming much wider due to rapid advance of CPU technology. By devising data structures and algorithms that utilize the behavior of the cache in CPU, we are able to enhance the overall performance of MMDBMSs considerably. In this paper, we address the practical implementation issues and our solutions for them obtained in developing the cache-conscious index manager of the Tachyon. The main issues touched are (1) consideration of the cache behavior, (2) compact representation of the index entry and the index node, (3) support of variable-length keys, (4) support of multiple-attribute keys, (5) support of duplicated keys, (6) definition of the system catalog for indexes, (7) definition of external APIs, (8) concurrency control, and (9) backup and recovery. We also show the effectiveness of our approach through extensive experiments.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.1
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• pp.11-23
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• 2022

Collaboration tools are used widely as non-face-to-face work increases due to social distancing after COVID-19. The tools are being developed in a cross-platform manner with 'Electron', an open source framework based on Chromium, to ensure accessibility on multiple devices. Electron Apps, applications built with Electron framework, store data in a manner similar to Chromium-based web browsers, so the data can be acquired in the same way as the data is acquired from a web browser. In this paper we analyze the data structure of web storage and suggest a method to get the message from Electron Apps focused on collaboration tools such as Jandi, Slack, and Microsoft Teams. For Jandi, we get the message from Cache by using previously developed tools, and in the case of Slack and Microsoft Teams, we get the message from IndexedDB by using the message carving tool we developed.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).