• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.149-156
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• 2010

As following the development of the USN technology, sensor node used in sensor network has capability of quick data process and storage to support efficient network configuration is enabled. In addition, tree-based structure was transformed to cluster in the construction of sensor network. However, query processing based on existing tree structure could be inefficient under the cluster-based network. In this paper, we suggest energy efficient query processing mechanism using filtering through data attribute classification in cluster-based sensor network. The suggestion mechanism use advantage of cluster-based network so reduce energy of query processing and designed more intelligent query dissemination. And, we prove excellence of energy efficient side with MATLab.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.2
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• pp.102-110
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• 2009

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1066-1077
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• 2004

Dramatic increase in the number of Internet users want highly qualified service of continuous media contents on the web. To solve these problems, we present two network caching schemes(PPC, PPCwP) which consider the characteristics of continuous media objects and user access pattern in this paper. While there are plenty of reasons to create rich media contents, delivering this high bandwidth contents over the internet presents problems such as server overload, network congestion and client-perceived latency. PPC scheme periodically calculates the popularity of objects based on the playback quantity and determines the optimal size of the initial fraction of a continuous media object to be cached in proportion to the calculated popularity. PPCwP scheme calculates the expected popularity using the series information and prefetches the expected initial fraction of newly created continuous media objects. Under the PPCwP scheme, the initial client-perceived latency and the data transferred from a remote server can be reduced and limited cache storage space can be utilized efficiently. Trace-driven simulation have been performed to evaluate the presented caching schemes using the log-files of iMBC. Through these simulations, PPC and PPCwP outperforms LRU and LFU in terms of BHR and DSR.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.46-54
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• 2018

The Internet of Things (IoT) is an environment in which various devices provide services to users through communications. Because of the nature of the IoT, data are stored and distributed in heterogeneous information systems. In this situation, IoT end applications should be able to access data without having information on where the data are or what the type of storage is. This mechanism is called Service Discovery (SD). However, some problems arise, since the current SD architectures search for data in physical devices. First, turnaround time increases from searching for services based on physical location. Second, there is a need for a data structure to manage devices and services separately. These increase the administrator's service configuration complexity. As a result, the device-oriented SD structure is not suitable to the IoT. Therefore, we propose an SD structure called Name-based Service-centric Service Discovery (NSSD). NSSD provides name-based centralized SD and uses the IoT edge gateway as a cache server to speed up service discovery. Simulation results show that NSSD provides about twice the improvement in average turnaround time, compared to existing domain name system and distributed hash table SD architectures.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.1-10
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• 2010

Recently heterogeneous storage system such as hybrid hard disk drive (H-HDD) combining flash memory and magnetic disk is launched, according as the read performance of NAND flash memory is enhanced as similar to that of hard disk drive (HDD) and the power consumption of NAND flash memory is reduced less than that of HDD. However, the read and write operations of NAND flash memory are slower than those of rotational disk. Besides, serious overheads are incurred on CPU and main memory in the case that intensive write requests to flash memory are repeatedly occurred. In this paper, we propose the Least Frequently Used-Hot scheme that replaces the data blocks whose reference frequency of read operation is low and update frequency of write operation is high, and the data flushing scheme that rearranges the data blocks into the multi-zone of the rotation disk. Experimental results show that the execution time of the proposed method is 38% faster than those of conventional LRU and LFU block replacement schemes in I/O performance aspect and the proposed method increases the life span of Non-Volatile Cache 40% higher than those of conventional LRU, LFU, FIFO block replacement schemes.

• Journal of KIISE:Information Networking
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• v.27 no.3
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• pp.301-314
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• 2000

As the number of World Wide Web (Web) users grows, Web traffic continues to increase at an exponential rate. Currently, Web traffic is one of the major components of Internet traffic. Also, high bandwodth usage due to Web traffic is observed during peak periods while leaving bandwidth usage idle during off-peak periods. One of the solutions to reduce Web traffic and speed up Web access is through the use of Web caching. Unfortunately, Web caching has limitations for reducing network bandwidth usage during peak periods. In this paper, we focus our attention on the use of a prefetching algorithm for reducing bandwidth during peak periods by using off-peak period bandwidth. We propose a statistical, batch, proxy-side prefetching scheme that improves cache hit rate while only requiring a small amount of storage. Web objects that were accessed many times in previous 24 hours but would be expired in the next 24 hours, are selected and prefetched in our scheme. We present simulation results based on Web proxy and show that this prefetching algorithm can reduce peak time bandwidth using off-peak bandwidth.

• Journal of the Korea Society of Computer and Information
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• v.14 no.3
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• pp.41-49
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• 2009

Flash memory has become increasingly requestion for the importance and the demand as a storage due to its low power consumption, cheap prices and large capacity medium. This research is to design a high performance flash memory structure for the substitution of a hard-disk by dynamic prefetching of aggressive spatial locality from the spatial smart buffer system. The proposed buffer system in a NAND flash memory consists of three parts, i.e., a fully associative victim buffer for temporal locality, a fully associative spatial buffer for spatial locality, and a dynamic fetching unit. We proposed new dynamic prefetching algorithm for aggressive spatial locality. That is to use the flash memory instead of the hard disk, the proposed flash system can achieve better performance gain by overcoming many drawbacks of the flash memory by the new structure and the new algorithm. According to the simulation results, compared with the smart buffer system, the average miss ratio is reduced about 26% for Mediabench applications. The average memory access times are improved about 35% for Mediabench applications, over 30% for Spec2000 applications.