• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.663-674
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• 2005

We propose a system aimed at achieving high energy-delay efficiency by using adaptive victim caches. Particularly, we investigate methods to improve the hit rates in the first level of memory hierarchy, which reduces the number of accesses to mort power consuming memory structures such as L2 cache. Victim cache is a memory element for reducing conflict misses in a direct-mapped L1 cache. We present two techniques to fill the victim cache with the blocks that have higher probability to be re-reqeusted by processor. Hit-based victim cache ks tilled with the blocks which were referenced frequently by processor. Replacement-based victim cache is filled with the blocks which were evicted from the sets where block replacements had happened frequently According to our simulations, replacement-based victim cache scheme outperforms the conventional victim cache scheme about $2\%$ on average and refutes the power consumption by up to $8\%$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.375-381
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• 2007

This paper focuses on the prediction algorithm among the context-awareness technologies. With a representative algorithm, Bayesian Networks, it is difficult to realize a context-aware as well as to decrease process time in real-time environment. Moreover, it is also hard to be sure about the accuracy and reliability of prediction. One of the simplest algorithms is the sequential matching algorithm. We use it by adding the proposed Cache Scheme. It is adequate for a context-aware service adapting user's habit and reducing the processing time by average 48.7% in this paper. Thus, we propose a design method of user location prediction algorithm that uses sequential matching with the cache scheme by taking user's habit or behavior into consideration. The novel approach will be dealt in a different way compared to the conventional prediction algorithm.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.41-48
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• 2012

A Vehicular Ad-hoc Network (VANET) is a vehicular specific type of a mobile ad-hoc network, to provide temporary communications among nearby vehicles. Mobile node of VANET consumes energy and resource with participating in the member of network. In a VANET, data replication and cooperative caching have been used as promising solutions to improve system performance. Existing cooperative caching scheme in a VANET mostly focuses on weak consistency is not always satisfactory. In this paper, we propose an efficient cache management scheme to maintain strong data consistency in a VANET. We make an adaptive scheduling scheme to broadcast Invalidation Report (IR) in order to reduce query delay and communication overhead to maintain strong data consistency. The simulation result shows that our proposed method has a strength in terms of query delay and communication overhead.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.32-38
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• 2015

In this paper, we propose a smallcell local caching algorithm under user's context in smallcell environment. The proposed system reduces traffic to core network and the network cost, but increases it's performance. The proposed algorithm precache suitable files using smallcell's regional characteristics and target's personality. It can adjusts a storage allocation to make effective usage of our limited cache storage capacity. In order to evaluate the performance of the proposed cache algorithm, we define the cache efficiency, the decrement of core network traffic. The simulation results show that the proposed algorithm can improve performance by about 200% compared to existing web cache scheme.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Journal of KIISE:Databases
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• v.29 no.2
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• pp.148-157
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• 2002

Caching in meta-search engines can improve the response time of users' request. We describe the cache scheme in our meta-search engine in terms of its architecture and operational flow. In particular, we propose a popularity-driven cache algorithm that utilizes popularities of queries to determine cached data to be purged. The popularity is a value that represents the normalized occurrence frequency of user queries. This paper presents how to collect popular queries and how to calculate query popularities. An empirical performance evaluation of the popularity-driven caching with the traditional schemes (i.e., least recently used (LRU) and least frequently used (LFU)) has been carried out on a collection of real data. In almost all cases, the proposed replacement policy outperforms LRU and LFU.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.125-131
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• 2006

This Paper proposes a new directory-based cache coherence scheme which significantly reduces coherence traffic by omitting unnecessary write-backs to home nodes for migratory exclusively-modified data. The proposed protocol is well matched to such migratory data which are accessed in turn by processors, since write-backs to home nodes are never used for such migratory sharing. The simulation result shows that our protocol dramatically alleviate the coherence traffic, and the traffic reduction could also lead to shorten network latency and execution time.

• Convergence Security Journal
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• v.12 no.4
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• pp.91-96
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• 2012

MANET is developed technique fairly among many field of wireless network. Nodes which consist of MANET transmit data using multi-hop wireless connection. Caching scheme is technique which can improve data access capacity and availability of nodes. Previous studies were achieved about dynamic routing protocol to improve multi-hop connection of moving nodes. But management and maintenance of effective cache information because of movement of nodes is not easy. In this study, we proposed cluster-based caching scheme to manage connection by decreasing overhead and moving of nodes as moving node discovers cache of wish information. And HLP was used to maintain effective cache table in each cluster head. Efficiency of proposed technique in this study was confirmed by experiment.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.142-150
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• 2021

Open-channel SSD is a new type of Solid-State Disk (SSD) that improves the garbage collection overhead and write amplification due to physical constraints of NAND flash memory by exposing the internal structure of the SSD to the host. However, the host-level Flash Translation Layer (FTL) provided for open-channel SSDs in the current Linux kernel consumes host memory excessively because it use page-level mapping table to translate logical address to physical address. Therefore, in this paper, we implemente a selective mapping table loading scheme that loads only a currently required part of the mapping table to the mapping table cache from SSD instead of entire mapping table. In addition, to increase the hit ratio of the mapping table cache, filesystem information and mapping table access history are utilized for cache replacement policy. The proposed scheme is implemented in the host-level FTL of the Linux kernel and evaluated using open-channel SSD emulator. According to the evaluation results, we can achieve 80% of I/O performance using the only 32% of memory usage compared to the previous host-level FTL.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.24-27
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• 2007

주기억 색인 기법인 Tmr-트리가 R-트리에 비해서 삽입시간이 오래 걸린다는 단점이 있다. 본 논문은 L2 캐시를 최대한 활용하여 기존 Tmr-트리의 장점을 가지는 새로운 CSTmr-트리(Cache Sensitive Tmr-트리)구조를 제안하고, 이 구조에 삽입, 삭제 등의 알고리즘을 제안하였다. 제안한 구조와 알고리즘을 다른 인덱스 구조와 비교하여 CSTmr-트리의 우수성을 보인다.