• Journal of the Korean Data and Information Science Society
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• v.20 no.6
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• pp.1177-1190
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• 2009

In this paper, we propose a fuzzy proxy cache scheme for caching web documents in mobile base stations. In this scheme, a mobile cache model is used to facilitate data caching and data replication. Using the proposed cache scheme, the individual proxy in the base station makes cache decisions based solely on its local knowledge of the global cache state so that the entire wireless proxy cache system can be effectively managed without centralized control. To improve the performance of proxy caching, the proposed cache scheme predicts the direction of movement of mobile hosts, and uses various cache methods for neighboring proxy servers according to the fuzzy-logic-based control rules based on the membership degree of the mobile host. The performance of our cache scheme is evaluated analytically in terms of average response delay and average energy cost, and is compared with that of other mobile cache schemes.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.35-44
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• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.9-16
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• 2017

In recent computing systems, LRU replacement policy has been widely used because it can be simply implemented and applicable to most programs. However, if the working set size of the program is bigger than the actual cache size, LRU replacement policy may occur thrashing problem. Thrashing problem means that cache blocks are consistently replaced without re-referencing in the cache. This paper proposes a new cache management scheme to solve the thrashing problem in the second-level cache. The proposed scheme measures per set reuse frequency using EAF structure to find thrashing sets. When the cache miss occurs, it tests whether the address of the missed block is stored or not. If the address of the missed block is stored, it means that the recently evicted block is re-requested, so the reuse frequency is predicted high. In this case, the corresponding counter of the set is increased. When the counter value is bigger than the threshold value, we assume that the corresponding set shows high reuse frequency. The proposed scheme assigns the set with high reuse frequency to the additional small size cache to keep the blocks in the cache for a long time. Our experimental results show that the proposed scheme improves the IPC by 3.81% on average.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.20-31
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• 2014

Recently, cache sharing methods have been studied in order to effectively reply to user requests in mobile P2P networks. In this paper, we propose a cache sharing scheme based on a cluster considering the peer connectivity in mobile P2P networks. The proposed scheme shares caches by making a cluster that consists of peers preserving the connectivity among them for a long time. The proposed scheme reduces data duplication to efficiently use the cache space in a cluster. The cache space is divided into two parts with a data cache and a temporary cache for a cache space. It is possible to reduce the delay time when the cluster topology is changed or the cache data is replaced utilizing a temporary cache. The proposed scheme checks the caches of peers in a route to a cluster header and the caches of one-hop peers in order to reduce the communication cost. It is shown through performance evaluation that the proposed scheme outperforms the existing schemes.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.324-336
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• 2000

The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Journal of KIISE
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• v.42 no.8
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• pp.972-978
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• 2015

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

• The Journal of Korean Institute of Next Generation Computing
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• v.14 no.5
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• pp.40-52
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• 2018

Solid state drive (SSD) cache technologies that are used as a second-tier cache between the main memory and hard disk drive (HDD) have been widely studied. The SSD cache requires a new prefetching scheme as well as cache replacement algorithms. This paper presents a prefetching scheme for a storage-class cache using SSD. This prefetching scheme is designed for the storage-class cache and based on a long-term scheduling in contrast to the short-term prefetching in the main memory. Traditional prefetching algorithms just consider only read, but the presented prefetching scheme considers both read and write. An experimental evaluation shows 2.3% to 17.8% of hit rate with a 64GB of SSD and the 4GiB of prefetching size using an I/O trace of 14 days. The proposed prefetching scheme showed significant improvement of cache hit rate and can be easily implemented in storage-class cache systems.

• Journal of KIISE:Databases
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• v.34 no.3
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• pp.217-231
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• 2007

Frequent disconnection is connected directly to client's cache consistency problem in Mobile Computing environment. For solving cache consistency problem, research about Invalidation Report is studied. But, existent invalidation report structure comes with increase of size of invalidation report structure and decline of cache efficiency if quantity of data become much, or quantity of updated data increases. Also, while existent method confirms whole cache, invalidation report doesn't support selective listening. This paper proposes TTCI(Timestamp Tree-based Cache Invalidation scheme) as invalidation report structure that solve problem of these existing schemes and improve efficiency. We can make TTCI using timestamp of updated data, composing timestamp tree and list ID of data in updated order. If we utilize this, each client can confirm correct information in point that become own disconnecting and increase cache utilization ratio. Also, we can pare down client's resources consumption by selective listening using tree structure. We experimented in comparison with DRCI(Dual-Report Cache Invalidation) that is existent techniques to verify such efficiency of TTCI scheme.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.