• Title/Summary/Keyword: cache replacement

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A Popularity-driven Cache Management and its Performance Evaluation in Meta-search Engines (메타 검색 엔진을 위한 인기도 기반 캐쉬 관리 및 성능 평가)

  • Hong, Jin-Seon;Lee, Sang-Ho
    • Journal of KIISE:Databases
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    • v.29 no.2
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    • pp.148-157
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    • 2002
  • Caching in meta-search engines can improve the response time of users' request. We describe the cache scheme in our meta-search engine in terms of its architecture and operational flow. In particular, we propose a popularity-driven cache algorithm that utilizes popularities of queries to determine cached data to be purged. The popularity is a value that represents the normalized occurrence frequency of user queries. This paper presents how to collect popular queries and how to calculate query popularities. An empirical performance evaluation of the popularity-driven caching with the traditional schemes (i.e., least recently used (LRU) and least frequently used (LFU)) has been carried out on a collection of real data. In almost all cases, the proposed replacement policy outperforms LRU and LFU.

Effective Algorithm for the Low-Power Set-Associative Cache Memory (저전력 집합연관 캐시를 위한 효과적인 알고리즘)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.1
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    • pp.25-32
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    • 2014
  • In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

Design and Implementation of Buffer Cache for EXT3NS File System (EXT3NS 파일 시스템을 위한 버퍼 캐시의 설계 및 구현)

  • Sohn, Sung-Hoon;Jung, Sung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.12
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    • pp.2202-2211
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    • 2006
  • EXT3NS is a special-purpose file system for large scale multimedia streaming servers. It is built on top of streaming acceleration hardware device called Network-Storage card. The EXT3NS file system significantly improves streaming performance by eliminating memory-to-memory copy operations, i.e. sending video/audio from disk directly to network interface with no main memory buffering. In this paper, we design and implement a buffer cache mechanism, called PMEMCACHE, for EXT3NS file system. We also propose a buffer cache replacement method called ONS for the buffer cache mechanism. The ONS algorithm outperforms other existing buffer replacement algorithms in distributed multimedia streaming environment. In EXT3NS with PMEMCACHE, operation is 33MB/sec and random read operation is 2.4MB/sec. Also, the buffer replacement ONS algorithm shows better performance by 600KB/sec than other buffer cache replacement policies. As a result PMEMCACHE and an ONS can greatly improve the performance of multimedia steaming server which should supportmultiple client requests at the same time.

Advanced Victim Cache with Processor Reuse Information (프로세서의 재사용 정보를 이용하는 개선된 고성능 희생 캐쉬)

  • Kwak Jong Wook;Lee Hyunbae;Jhang Seong Tae;Jhon Chu Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.12
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    • pp.704-715
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    • 2004
  • Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

Cache Replacement Strategies considering Location and Region Properties of Data in Mobile Database Systems (이동 데이타베이스 시스템에서 데이타의 위치와 영역 특성을 고려한 캐쉬 교체 기법)

  • Kim, Ho-Sook;Yong, Hwan-Seung
    • Journal of KIISE:Databases
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    • v.27 no.1
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    • pp.53-63
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    • 2000
  • The mobile computing service market is increasing rapidly due to the development of low-cost wireless network technology and the high-performance mobile computing devices. In recent years, several methods have been proposed to effectively deal with restrictions of the mobile computing environment such as limited bandwidth, frequent disconnection and short-lived batteries. Amongst those methods, much study is being done on the caching method - among the data transmitted from a mobile support station, it selects those that are likely to be accessed in the near future and stores them in the local cache of a mobile host. Existing cache replacement methods have some limitations in efficiency because they do not take into consideration the characteristics of user mobility and spatial attributes of geographical data. In this paper, we show that the value and the semantic of the data, which are stored in the cache of a mobile host, changes according to the movement of the mobile host. We argue it is because data that are geographically near are better suited to provide an answer to a users query in the mobile environment. Also, we define spatial location of geographical data has effect on, using the spatial attributes of data. Finally, we propose two new cache replacement methods that efficiently support user mobility and spatial attributes of data. One is based on the location of data and the other on the meaningful region of data. From the comparative analysis of the previous methods and that they improve the cache hit ratio. Also we show that performance varies according to data density using this, we argue different cache replacement methods are required for regions with varying density of data.

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Cache Replacement and Coherence Policies Depending on Data Significance in Mobile Computing Environments (모바일 컴퓨팅 환경에서 데이터의 중요도에 기반한 캐시 교체와 일관성 유지)

  • Kim, Sam-Geun;Kim, Hyung-Ho;Ahn, Jae-Geun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.2A
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    • pp.149-159
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    • 2011
  • Recently, mobile computing environments are becoming rapidly common. This trend emphasizes the necessity of accessing database systems on fixed networks from mobile platforms via wireless networks. However, it is not an appropriate way that applies the database access methods for traditional computing environments to mobile computing environments because of their essential restrictions. This paper suggests a new agent-based mobile database access model and also two functions calculating data significance scores to choose suitable data items for cache replacement and coherence policies. These functions synthetically reflect access term, access frequency and tendency, update frequency and tendency, and data item size distribution. As the result of simulation experiment, our policies outperform LRU, LIX, and SAIU policies in aspects of decrement of access latency, improvement of cache byte hit ratio, and decrease of cache byte pollution ratio.

Design of a DI model-based Content Addressable Memory for Asynchronous Cache

  • Battogtokh, Jigjidsuren;Cho, Kyoung-Rok
    • International Journal of Contents
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    • v.5 no.2
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    • pp.53-58
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    • 2009
  • This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

Cache Replacement Policies Considering Small-Writes and Reference Counts for Software RAID Systems (소프트웨어 RAID 파일 시스템에 작은 쓰기와 참조 횟수를 고려한 캐쉬 교체 정책)

  • Kim, Jong-Hoon;Noh, Sam-Hyuk;Won, Yoo-Hun
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.11
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    • pp.2849-2860
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    • 1997
  • In this paper, we present efficient cache replacement policies for the software RAID file system. The performance of this policies is compared to two other policies previously proposed for conventional file systems and adapted for the software RAID file system. As in hardware RAID systems, we found small-writes to be the performance bottleneck in software RAID file systems. To tackle this small-write problem, we propose cache replacement policies. Using trace driven simulations we show that the proposed policies improve performance in the aspect of the average response time and the average system busy time.

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Efficient Buffer Allocation Policy for the Adaptive Block Replacement Scheme (적응력있는 블록 교체 기법을 위한 효율적인 버퍼 할당 정책)

  • Choi, Jong-Moo;Cho, Seong-Je;Noh, Sam-Hyuk;Min, Sang-Lyul;Cho, Yoo-Kun
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.3
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    • pp.324-336
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    • 2000
  • The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

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Development of WWW cache replacement algorithm for the Internet data access (인터넷 데이터 접급 속도 향상을 위한 WWW 캐시 교환 알고리즘 개발)

  • Heo, Yeun-Jeong;Lee, Yang-Weon;Kim, Chul-Won
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.1085-1088
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    • 2005
  • 인터넷 사용자들의 증가와 함께 네트워크에서 데이터 교환량이 증가하고 있다. 따라서 네트워크 트래픽과 서버의 부담으로 인하여 WWW 서버로부터 응답 시간의 하락은 많은 문제로 제기되고 있다. 본 논문에서는 WWW cache 서버를 이용하여 응답시간을 줄수 있는 방안을 제시한다. 이런 목적을 위하여 www cache 서버를 원격으로 교체할 수 있는 알고리즘을 제안한다.

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