• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.9-17
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• 2003

In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature ($T_g$) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and $T_g$. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

• Journal of Life Science
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• v.22 no.10
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• pp.1277-1285
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• 2012

The tumor necrosis, factor-related, apoptosis-inducing ligand (TRAIL) is regarded as a potentially useful anticancer agent with excellent selectivity for cancer cells. However, a considerable number of cancer cells are resistant to apoptosis induction by TRAIL. Developing strategies to overcome this resistance are important for the successful use of TRAIL for cancer therapy. Here, we revealed that siRNA-mediated downregulation of SIRT1 or SIRT1 inhibitor Amurensin G upregulated DR5 and c-Myc and downregulated c-$FLIP_{L/S}$ and Mcl-1, which was associated with sensitization of TRAIL-resistant MCF-7 cells to TRAIL. This result was followed by the activation of caspases, PARP cleavage, and downregulation of Bcl-2 in both TRAIL-treated MCF-7 cells transfected with SIRT1 siRNA and cells co-treated with Amurensin G and TRAIL. Our results suggest that the induction of DR5 and downregulation of c-FLIP via suppression of SIRT1 expression may be a useful strategy to increase the susceptibility of TRAIL-resistant cancer cells to TRAIL-induced cell death.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.583-584
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• 2008

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.49-58
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• 1998

In this paper, we report new algorithms to select scan flip-flops for the no holding partial scan test method. The no holding partial scan test method is identical to the full scan test method except that some flip-flops are left unscanned. This test method does not hold scanned or unscanned flip-flops while shifting in test vectors, or applying them, or shifting out test results. The proposed algorithm allows a large number of flip-flops to be left unscanned while maintaining almost the complete full scan fault coverage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.

• Biomolecules & Therapeutics
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• v.23 no.1
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• pp.31-38
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• 2015

Histone acetylation plays a critical role in the regulation of transcription by altering the structure of chromatin, and it may influence the resistance of some tumor cells to tumor necrosis factor (TNF)-related apoptosis-inducing ligand (TRAIL) by regulating the gene expression of components of the TRAIL signaling pathway. In this study, we investigated the effects and molecular mechanisms of trichostatin A (TSA), a histone deacetylase inhibitor, in sensitizing TRAIL-induced apoptosis in Caki human renal carcinoma cells. Our results indicate that nontoxic concentrations of TSA substantially enhance TRAIL-induced apoptosis compared with treatment with either agent alone. Cotreatment with TSA and TRAIL effectively induced cleavage of Bid and loss of mitochondrial membrane potential (MMP), which was associated with the activation of caspases (-3, -8, and -9) and degradation of poly (ADP-ribose) polymerase (PARP), contributing toward the sensitization to TRAIL. Combined treatment with TSA and TRAIL significantly reduced the levels of the cellular Fas-associated death domain (FADD)-like interleukin-$1{\beta}$-converting enzyme (FLICE) inhibitory protein (c-FLIP), whereas those of death receptor (DR) 4, DR5, and FADD remained unchanged. The synergistic effect of TAS and TRAIL was perfectly attenuated in c-$FLIP_L$-overexpressing Caki cells. Taken together, the present study demonstrates that down-regulation of c-FLIP contributes to TSA-facilitated TRAIL-induced apoptosis, amplifying the death receptor, as well as mitochondria-mediated apoptotic signaling pathways.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.71-76
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• 2012

A chip interconnection technology for smart fabrics was investigated by using flip-chip bonding of SnBi low-temperature solder. A fabric substrate with a Cu leadframe could be successfully fabricated with transferring a Cu leadframe from a carrier film to a fabric by hot-pressing at $130^{\circ}C$. A chip specimen with SnBi solder bumps was formed by screen printing of SnBi solder paste and was connected to the Cu leadframe of the fabric substrate by flip-chip bonding at $180^{\circ}C$ for 60 sec. The average contact resistance of the SnBi flip-chip joint of the smart fabric was measured as $9m{\Omega}$.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.45-52
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• 2011

It is known that test methods to evaluate solder joint reliability are die shock test, die shear test, 3points bending test, and thermal shock test. The present study investigated the effects of failure mode on 3 types (as-reflowed, $85^{\circ}C$/85%RH treatment, and $150^{\circ}C$/10hr aging) of solder joints for flip-chip BGA package by using various test methods. The test methods and configurations are reported in detail, i.e. die shock, die shear, 3points bending, and thermal shock test. We focus on the failure mode of solder joints under various tests. The test results indicate that die shock and die shear test method can reveal brittle fracture in flip-chip ball grid array (FCBGA) packages with higher sensitivity.