• Journal of Korean Society of Transportation
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• v.17 no.4
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• pp.47-58
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• 1999

The Purpose of this Paper is to develop a multi-period bus scheduling model, in which a decomposition technique is applied. In general a bus scheduling requires a vast amount of calculation. Thus, a bus scheduling is a very complicated problem even with a single depot and is almost unable to obtain the optimal solution theoretically with many depots. In this paper in order to simplify the problem, the whole operating hours of a day are partitioned into several time periods. In one period, the same headways are maintained. For one period, the bus scheduling is simple and the solution applying the FIFO(First-In, First-Out) Principle is the optimal. However, connection between Periods remains as another scheduling Problem with a reduced problem size. This paper suggests how to connect bus schedules of consecutive periods efficiently, minimizing the operating cost. Through case studies for multiple routes with a single depot, this decomposition technique is proved to be effective practically.

• Journal of Korean Society of Transportation
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• v.28 no.5
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• pp.43-54
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• 2010

In order to improve the existing evaluation system of bus services and gain more reasonable analysis outputs, the authors evaluate the efficiency of 113 arterial bus routes in Seoul in 2009 using a modified BCC model considering not only desirable outputs but also undesirable outputs. Each Decision Making Unit (DMU) is assumed to use inputs such as possession costs, operating costs, the ratios of median bus stops overlapped route lengths to produce estimates of desirable outputs (the number of passengers and service satisfaction score) and undesirable outputs (CO2 emissions). According to the analysis, the modified BCC model considering both desirable outputs and undesirable outputs shows more appropriate results. DMUs would be more efficient on average to reduce nearly 10% of the 3 inputs (possession costs, operating costs, and overlapped route lengths) and increase by about 160% the ratios of median bus stops. Also, a Tobit regression analysis is conducted to identify the most effective variables for maximum efficiency and discover that the variable of possession costs and the ratios of median bus stops are statistically significant.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.32 no.3D
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• pp.213-222
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• 2012

After enforcing 2007 semi-public management system of intra-city bus, Busan city has tried to promote the bus utilization through bus service improvements. As an effort for this, we attempted to clarify the main factors affecting to bus service satisfaction targeting intra-city bus users. In this study, 20 subcategories of intra-city bus service were assorted into 6 factors: Basic Service, Safe Driving, Route Information, Comfort, Cleanliness and Facilities, then the preference for each detailed bus service were analyzed. And the effects for bus service satisfaction were shown under the various conditions according to the general characteristics of intra-city bus users (gender, age), behavioral traffic characteristics (frequency of use, boarding time) and transportation environments (temperature, rainfall). These results would be important basic data for decision-making in bus policy for climate change and establishment of operating plan for bus utilization.

• Journal of KIBIM
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• v.8 no.3
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• pp.12-19
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• 2018

The research aims to find implications of machine learning and urban big data as a way to construct the flexible transportation network system of smart city by responding the urban context changes. This research deals with a problem that existing a bus headway model is difficult to respond urban situations in real-time. Therefore, utilizing the urban big data and machine learning prototyping tool in weathers, traffics, and bus statues, this research presents a flexible headway model to predict bus delay and analyze the result. The prototyping model is composed by real-time data of buses. The data is gathered through public data portals and real time Application Program Interface (API) by the government. These data are fundamental resources to organize interval pattern models of bus operations as traffic environment factors (road speeds, station conditions, weathers, and bus information of operating in real-time). The prototyping model is implemented by the machine learning tool (RapidMiner Studio) and conducted several tests for bus delays prediction according to specific circumstances. As a result, possibilities of transportation system are discussed for promoting the urban efficiency and the citizens' convenience by responding to urban conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• KIEE International Transactions on Power Engineering
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• v.5A no.2
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• pp.177-185
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• 2005

This paper proposes an expert system that can enhance the accuracy of real-time bus reconfiguration strategy by adopting the local minimum tree search method and that can minimize the spreading effect of the fault by considering the operating condition when a main transformer fault occurs in an automated substation. The local minimum tree search method is used to expand the best-first search method. This method has the advantage that it can improve the solution performance within the limits of the real-time condition. The inference strategy proposed expert system consists of two stages. The first stage determines the switching candidate set by searching possible switching candidates starting from the main transformer or busbar related to the event. The second stage determines the rational real-time bus reconfiguration strategy based on heuristic rules from the obtained switching candidate set. Also, this paper proposes generalized distribution substation modeling using graph theory, and a substation database based on the study results is designed.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.24 no.3
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• pp.219-226
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• 2014

A bus duct system for wind tower is introduced. A marine cable has been widely used in wind tower or various offshore structures. However, as the electric load capacity is increases, large number of cable lines must be used to cover the huge amount of electric capacities. Therefore, the installation of the cable lines becomes very difficult due to the heavy weight and volume of the cables. On the other hand, by using a single bus duct system line, the power capacity amount of 16 cables can be delivered with significantly compacted form. However, unlike flexible cables, the bus duct is relatively stiff which could generate the resonance phenomenon in the operating condition of the wind tower. In this study, the vibration characteristics of the bus duct are investigated and its long-term reliability during the life time of the wind tower is verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.