• ETRI Journal
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• v.32 no.5
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• pp.713-721
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• 2010

E-textile technology has earned a great deal of interest in many fields; however, existing wearable network protocols are not optimized for use with conductive yarn. In this paper, some of the basic properties of conductive textiles and requirements on wearable personal area networks (PANs) are reviewed. Then, we present a wearable personal network (WPN), which is a four-layered wearable PAN using bus topology. We have designed the WPN to be a lightweight protocol to work with a variety of microcontrollers. The profile layer is provided to make the application development process easy. The data link layer exchanges frames in a master-slave manner in either the reliable or best-effort mode. The lower part of the data link layer and the physical layer of WPN are made of a fabric serial-bus interface which is capable of measuring bus signal properties and adapting to medium variation. After a formal verification of operation and performances of WPN, we implemented WPN communication modules (WCMs) on small flexible printed circuit boards. In order to demonstrate the behavior of our WPN on a textile, we designed a WPN tutorial shirt prototype using implemented WCMs and conductive yarn.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.414-417
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• 2001

In this paper the fuel filling system for a city bus was investigated in order to improve the system. The suggested fuel filling system was designed to have functions of identifying a bus arrival tine, and measuring volume of fuel filled. The system consisted of four parts of bus identification, IBM PC, interface card, fuel filling control system and program for integrating all parts. It is believed that the information obtained by this system can be used for analysing driver's driving habits and performance of engine of a bus, and accordingly the prime cost can be reduced.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.313-319
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• 2006

This paper addresses improving the voltage stability limit of interface flow between two different regions in an electric power system using the Static Synchronous Series Compensator (SSSC). The paper presents a power flow analysis model of a SSSC, which is obtained from the injection model of a series voltage source inverter by adding the condition that the SSSC injection voltage is in quadrature with the current of the SSSC-installed transmission line. This model is implemented into the modified continuation power flow (MCPF) to investigate the effect of SSSCs on the interface flow. A methodology for determining the interface flow margin is simply briefed. As a case study, a 771-bus actual system is used to verify that SSSCs enhance the voltage stability limit of interface flow.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.493-496
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• 2005

The PMU (Payload Management Unit) in MSC (Multi-Spectral Camera) is the main subsystem for the management, control and power supply of the MSC payload operation. The PMU shall handle the communication with the BUS (Spacecraft) OBC (On Board Computer) for the command, the telemetry and the communications with the various MSC units. The PMU will perform that distributes power to the various MSC units, collects the telemetry reports from MSC units, performs thermal control of the EOS (Electro-Optical Subsystem), performs the NUC (Non-Uniformity Correction) function of the raw imagery data, and rearranges the pixel data and output it to the DCSU (Data Compression and Storage Unit). The BUS provides high voltage to the MSC. The PMU is connected to primary and redundant BUS power and distributes the high unregulated primary voltages for all MSC sub-units. The PSM (Power Supply Module) is an assembly in the PMU implements the interface between several channels on the input. The bus switches are used to prevent a single point system failure. Such a failure could need the PSS (Power Supply System) requirement to combine the two PSM boards' bus outputs in a wired-OR configuration. In such a configuration if one of the boards' output gets shorted to ground then the entire bus could fail thereby causing the entire MSC to fail. To prevent such a short from pulling down the system, the switch could be opened and disconnect the short from the bus. This switch operation is controlled by the BUS.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.6
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• pp.620-628
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• 2010

Small satellites can be used for various space research and scientific or educational purposes due to advantages in small size, low-cost, and rapid development. Small Satellites have many advantages of application to Responsive Space. Compared to traditional larger satellites, however, Small satellites have many constraints due to limitations in size. Therefore, it is difficult to expect high performance. To approach maximum capability with minimal size, weight, and cost, standard modular platform of Small satellites is necessary. Modularity supports plug-and-play architecture. The result is Small satellites that can be combined quickly and reliably using plug-and-play mechanisms. For communication between modules, standard bus interface is needed. Controller Area Network(CAN) protocol is considered optimum data bus for modular Small satellite. CAN can be applied to data communication with high reliability. Hence, design optimization and simplification can also be expected. For ease of assembly and integration, modular design can be considered. This paper proposes development method for standardized modular Small satellites, and describes design of data interface based on CAN and a method of testing for modularity.

• The KIPS Transactions:PartA
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• v.13A no.6 s.103
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• pp.495-500
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• 2006

The role of autonomic and intelligent agents in various environments is getting more important as demand on ubiquitous computing grows. The agents exchange information using the ACL (Agent Communication Language) to autonomously solve the problems. In this paper we propose a way of efficient interoperability technique between the agent framework built based on the international standard FIPA(Foundation for Intelligent Physical Agents) and the CORBA event service-based information bus adapter developed by us. The design and implementation of EMTI (Efficient Message Transport Interface) allowing communication between the information bus adapter which is non-agent platform and JADE platform are presented and its performance is evaluated by letting them exchange a large amount of messages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• ETRI Journal
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• v.34 no.4
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• pp.553-563
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• 2012

Serial peripheral interface (SPI) has been identified as a bottleneck in many wireless sensing systems today. SPI is used almost universally as the physical connection between the microcontroller unit (MCU) and radios, storage devices, and many types of sensors. Virtually all wireless sensor nodes today perform up to twice as many bus transactions as necessary to transfer a given piece of data, as an MCU must serve as the bus master in all transactions. To eliminate this bottleneck, we propose the master-handoff protocol. After the MCU initiates reading from the source slave device and writing to the sink slave device, the MCU as a master becomes a slave, and either the source or the sink slave becomes the temporary master. Experiment results show that this master-handoff technique not only cuts the data transfer time in half, but, more importantly, also enables a superlinear energy reduction.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.45-47
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• 2000

본 연구는 심볼릭 모델 체커 중의 하나인 SMV(Symbolic Model Verifier)를 이용하여 한국전자통신연구원(ETRI)에서 개발한 CCA(Cache Coherent Agent) 보드를 위한 I-Link Bus(Inside Bus)의 몇 가지 특성(property)들을 검증하여 I-Link Bus의 요구사항(requirement)이 만족됨을 보인다. 이 검증에서는 I-Link Bus의 모델을 SMV 입력 언어로 명세하며, 검증할 특성들을 시제 논리(temporal logic)를 이용하여 나타낸다. 검증을 통해서 I-Link Bus와 PIF(Processor Interface), DC(Directory Controller), RC(Remote access cache Controller)모듈들이 중재기 우선 순위, send 우선 순위, 중재 요청 신호의 관리, liveness등의 특성들을 만족한다라는 것을 검증하였다.