• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.55-57
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• 2007

A Power control and Distribution Unit (PCDU) plays roles of protection of battery against overcharge by active control of solar array generated power, distribution of unregulated electrical power via controlled outlets to bus and instrument units, distribution of regulated electrical power to selected bus and instrument units, and provision of status monitoring and telecommand interface allowing the system and ground operate the power system, evaluate its performance and initiate appropriate countermeasures in case of abnormal conditions. In this work, we perform the preliminary design of a PCDU for the small Low Earth Orbit (LEO) Satellite applications. The main constitutes of the PCDU are the battery interface module, solar array regulators with maximum power point tracking (MPPT) technology, heater power distribution modules, internal converter modules for regulated bus voltage generation, power distribution modules of unregulated and regulated primary bus, and instrument power distribution modules.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.10a
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• pp.239-242
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• 2009

Power Control and Distribution Unit (PCDU) plays roles of power generation control for solar array panel, power storage control for battery system, power conversion for unregulated and regulated primary bus and power distribution to bus and payload system. The selection and design of the proper auxiliary power interface for PCDU depending on various mission is one of the most important step for electrical power subsystem design. In this paper, the general design approach of auxiliary power interface for PCDU which can be used for small-sized LEO satellites application is given. And, the auxiliary power design concept for always alived modules such as solar array regulator and house keeping module is also suggested.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.123-131
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• 2002

ASC(Avionics System Computer) was developed to control weapon delivery and navigation sensors, and to perform man-machine interface with pilots for XKO-1 aircraft. The data communications between ASC and UFC(Up Front Controller), DC(Data Concentrator) were implemented by RS422 serial data bus. Also, SCIL(Standard Computer Interface Library) was designed to facilitate control and management of the computer hardware resources and is embedded in the ASC. These structures have a merit of noise immunity and a reduction of wire harness for signal lines, and enable OFP(Operational Flight Program) programmers to use the SCIL easily without knowing hardware details. Manufactured system was on installed on XKO-1, and peformed for BIT(Built In Test) and interface test with UFC and DC. The test results show that it meets the system requirements.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.573-580
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• 2002

Reusing IPs requires interface protocol related tasks such as writing test benches and designing interface protocol conversion circuits, e.g. wrappers for IPs. The results of those tasks usually include IPC(interface protocol component)s for the corresponding IPs, similar to bus protocol components of the bus functional models. This paper proposes a methodology for the interface circuit design using synthesizable In that can be re-used. IPC recognizes or executes transactions over the given interface ports. So we present a transaction-oriented interface protocol description language, and a method to convert the description into an IPC in synthesizable VHDL code. With experiments, we show that the interface design using IPC does not cause significant area overhead compared with the interface design without IPC. The proposed IPC-based approach can be employed to reduce the interface design time since the designers can reuse IPCs without understanding the detailed interface protocols.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2499-2502
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• 2005

Universal Serial Bus (USB) is one of the most popular communication interfaces. When USB is used in more extended range, especially configuring home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of Time Division Multiplexing (TDM) so that the bottleneck of bus bandwidth can be brought under the heavy traffic. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced. Basically, in order to realize the system for transferring real-time moving picture data among digital information devices, we analyze USB transfer types and descriptors and introduce the method to enhance the detailed performance of isochronous transfer that is one of USB transfer types.