• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1045-1054
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• 2006

In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• Journal of the Korean Society of Marine Environment & Safety
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• v.20 no.3
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• pp.318-322
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• 2014

A kind of field bus called Actuator and Sensor interface bus(AS-i) was designed in this paper. The configuration of AS-i network system used Application Specific Integrated Circuit(ASIC) SAP5S chip and PLC S7-200 station, which included CPU 224 and AS-i master module CP 243-2. We also created an example program for PLC S7-200 to control AS-i network. The fire and smoke detection system was made with AS-i network system that was designed. This system had got more advantages than other system such as number of stations, easy installation, wide working area, etc. And designed system can be used as a partner network for higher level field bus networks.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.193-194
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• 2008

This paper defines the electrical interfaces and limited items to integrate Ka-band communication payload on the satellite system, which includes the detailed interfaces such as bus voltage and data bus according to the related COMS requirements. And the BUS Electrical Interface Simulator introduces to use during the course of validating and accepting between the KA-Band payload and their EGSE. These interface design results are fully validated through the testing with the BEIS and is compliant with the satellite interface control interface requirements.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1836-1839
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• 2005

We have developed Ethernet based real-time communication systems called "Vnet/IP" for DCS which is the control system for process automation. This paper describes the features and the technologies of the ASIC which is utilized in the communication interface hardware for Vnet/IP. Vnet/IP has been developed for mission-critical communications. Hence it has real-time feature, high reliability and precise time synchronization capability. At the same time, it is able to deal with standard protocols without influence on mission-critical communications. The communication interface hardware has a host interface and dual redundant network interfaces. The host interface can be chosen PCI-bus or R-bus which is the proprietary internal bus developed for the high reliable redundant controller. Each network interface is a RJ45 connection with 1Gbps maximum in compliance with IEEE802.3.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.390-398
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• 2004

This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.