• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• 한국세라믹학회지
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• 제49권6호
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• pp.637-641
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• 2012

Due to its high production cost and relatively high energy consumption during the Siemens process, poly-silicon makers have been continuously and eagerly sought another silicon route for decades. One candidate that consumes less energy and has a simpler acidic and metallurgical purification procedure is upgraded metallurgical-grade (UMG) silicon. Owing to its low purity, UMG silicon often requires special steps to minimize the impurity effects and to remove or segregate the metal atoms in the bulk and to remove interfacial defects such as precipitates and grain boundaries. A process often called the 'gettering process' is used with phosphorus diffusion in this experiment in an effort to improve the performance of silicon solar cells using UMG silicon. The phosphorous gettering processes were optimized and compared to the standard POCl process so as to increase the minority carrier lifetime(MCLT) with the duration time and temperature as variables. In order to analyze the metal impurity concentration and distribution, secondary ion mass spectroscopy (SIMS) was utilized before and after the phosphorous gettering process.

• 대한전자공학회논문지
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• 제15권4호
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• pp.26-32
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• 1978

실리콘 태양전지의 수명을 예측하기 위하여 1 MeV electron radiation으로 인한 실리콘 손상을 조사 연구하였다. 그 결과 흑형 실리콘에 있어서는 거의 안정상태의 손상에 이르렀음을 보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• Interaction and multiscale mechanics
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• 제1권2호
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• pp.303-315
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• 2008

In this paper, thermodynamical properties of crystalline silicon under strain are calculated using classical molecular dynamics (MD) simulations based on the Tersoff interatomic potential. The Helmholtz free energy of the silicon crystal under strain is calculated by using the ensemble method developed by Frenkel and Ladd (1984). To account for quantum corrections under strain in the classical MD simulations, we propose an approach where the quantum corrections to the internal energy and the Helmholtz free energy are obtained by using the corresponding energy deviation between the classical and quantum harmonic oscillators. We calculate the variation of thermodynamic properties with temperature and strain and compare them with results obtained by using the quasi-harmonic model in the reciprocal space.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.162-165
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• 1991

Oxygen behaviors in CZ-silicon wafer, grown by the Lucky Advanced Materials Inc. that is a pioneer of silicon material industries in Korea, were investigated to simulate effects on the device performance of oxygen, neglecting the effect of other impurity content, defects and thermal history. Silicon wafers were annealed through simulated 16K SRAM thermal cycle. As initial oxygen concentration increased up to 16.7ppma the amount of oxygen precipitation increased up to 10.6ppma and the bulk microdefect density increased up to $10.3{\times}10^3/mm^2$, but the depth of the denuded zone decreased to $5.0{\mu}m$

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1054-1056
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• 2002

High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

• 전자통신동향분석
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• 제33권6호
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• pp.1-11
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• 2018

Several industrial applications such as space exploration, aerospace, automotive, the downhole oil and gas industry, and geothermal power plants require specific electronic systems under extremely high temperatures. For the majority of such applications, silicon-based technologies (bulk silicon, silicon-on-insulator) are limited by their maximum operating temperature. Silicon carbide (SiC) has been recognized as one of the prime candidates for providing the desired semiconductor in extremely high-temperature applications. In addition, it has become particularly interesting owing to a Si-compatible process technology for dedicated devices and integrated circuits. This paper briefly introduces a variety of SiC-based integrated circuits for use under extremely high temperatures and covers the technology trend of SiC CMOS devices and processes including the useful implementation of SiC ICs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• 한국결정성장학회지
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• 제11권3호
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• pp.89-95
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• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.