• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2504-2508
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• 1998

In this paper, we propose the new detecting method for three dimensional piezoresistive silicon accelerometer. Furthermore the accelerometer is formed to have endurance for high temperature by perfect isolation of the piezoresistors using Silicon On Insulator(SOI) wafer. Sensor size are optimized with analytical formulae and extended with FEM simulation for the more detailed results. The accelerometer was fabricated by bulk micromachining techonology. We measured the temperature characteristics and the output characteristics, and the both characteristics were compared with the simulated results

• 한국세라믹학회지
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• 제37권6호
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• pp.596-603
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• 2000

The hardness and elastic modulus of three bulk materials are computed from the load and displacement data which are measured during basic nanoindentation test and compared with values determined by independent means to assess the accuracy of the method. The results show that with this technique, modulus and hardness and elastic modulus profile through depth of silicon nitride and silicon oxynitride films. The results show that for silicon nitride film deposited on silicon, hardness and elastic modulus increase as the volume ratio of NH3 : SiH4, which had been used for deposition, increases up to 20.0; and for silicon oxynitride film on silicon, the hardness and elastic modulus profile changes distinctly as the relative amount of oxygen in deposition gas mixture changes.

• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.175-175
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• 2000

Si(100) surfaces were exposed to gas-phase thermal-energy hydrogen atoms, H(g). We find that thermal H(g) atoms etch, amorphize, or penetrate into the crystalline silicon substrate, depending on the employed Ts range during the H(g) exposure. We find that etching is enhanced as Ts is lowered in the 300-700K range, while amorphous silicon hydride (a-Si:H) formation dominates at a Ts below 300K. This result was well explained by the fact that formation of the etching precursor, SiHx(a), and amorphization are both facilitated by a lower Ts, whereas the final step for etching, SiH3(a) + H(g) longrightarrow SiH3(g), is suppressed at a lower Ts. we also find that direct absorption of H(g) by the crystalline bulk of Si(100) substrate occurs within a narrow Ts window of 420-530K. The bulk-absorbed hydrogen evolved out molecularly from Si(100) at a Ts 80-120K higher than that for surface monohydride phase ($\beta$1) in temperature-programmed desorption. This bulk-phase H uptake increased with increasing H(g) exposure without saturation within our experimental limits. Direct absorption of H(g) into the bulk lattice occurs only when the surface is atomically roughened by surface etching. While pre-adsorbed hydrogen atoms on the surface, H(a), were readily abstracted and replaced by D(g), the H atoms previously absorbed in the crystalline bulk were also nearly all depleted, albeit at a much lower rate, by a subsequent D(g) at the peak temperature in TPD from the substrate sequentially treated with H(g) and D(g), together with a gas phase-like H2 Raman frequency of 4160cm-1, will be presented.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권6호
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• pp.271-277
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• 2002

In this paper, a MEMS silicon package is newly designed, fabricated for HMIC, and characterized for microwave and millimeter-wave device applications. The proposed package is fabricated by using two high resistivity silicon substrates and surface/bulk micromachining technology. It has a good performance characteristic such as -20㏈ of $S_11$/ and -0.3㏈ of $S_21$ up to 20㎓, which is useful in microwave region. It has also better heat transfer characteristics than the commonly used ceramic package. Since the proposed silicon MEMS package is easy to fabricate and wafer level chip scale packaging is also possible, the production cost can be much lower than the ceramic package. Since it will be a promising low-cost package for mobile/wireless applications.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• 한국세라믹학회지
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• 제51권6호
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• pp.539-543
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• 2014

Foam type porous silicon carbide ceramics were fabricated by a polymer replica method using polyurethane foam, carbon black, phenol resin, and silicon powder as raw materials. The influence of the C/Si mole ratio of the ceramic slurry and heat treatment temperature on the porous silicon carbide microstructure was investigated. To characterize the microstructure of porous silicon carbide ceramics, BET, bulk density, X-ray Powder Diffraction (XRD), and Scanning Electron Microscope (SEM) analyses were employed. The results revealed that the surface area of the porous silicon carbide ceramics decreases with increased heat treatment temperature and carbon content at the $2^{nd}$ heat treatment stage. The addition of carbon to the ceramic slurry, which was composed of phenol resin and silicon powder, enhanced the direct carbonization reaction of silicon. This is ascribed to a consequent decrease of the wetting angles of carbon to silicon with increasing heat treatment temperature.

• 전기전자학회논문지
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• 제1권1호
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 전자통신동향분석
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• 제33권6호
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• pp.12-23
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• 2018

In this paper, we review the technical trends of diamond and gallium oxide ($Ga_2O_3$) semiconductor technologies among ultra-wide bandgap semiconductor technologies for harsh environments. Diamond exhibits some of the most extreme physical properties such as a wide bandgap, high breakdown field, high electron mobility, and high thermal conductivity, yet its practical use in harsh environments has been limited owing to its scarcity, expense, and small-sized substrate. In addition, the difficulty of n-type doping through ion implantation into diamond is an obstacle to the normally-off operation of transistors. $Ga_2O_3$ also has material properties such as a wide bandgap, high breakdown field, and high working temperature superior to that of silicon, gallium arsenide, gallium nitride, silicon carbide, and so on. In addition, $Ga_2O_3$ bulk crystal growth has developed dramatically. Although the bulk growth is still relatively immature, a 2-inch substrate can already be purchased, whereas 4- and 6-inch substrates are currently under development. Owing to the rapid development of $Ga_2O_3$ bulk and epitaxy growth, device results have quickly followed. We look briefly into diamond and $Ga_2O_3$ semiconductor devices and epitaxy results that can be applied to harsh environments.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.127-130
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• 1989

This paper reports the theoretical model and the experimental results regarding to the electrical conductivity of hydrogenated amorphous silicon (a-Si:H). The total effective conductance of a-Si:H with a planar structure has been considered as the sum of the conductance of an adsorbate-induced layer, a surface-interface layer, a bulk layer, and a substrate-interface layer. In order to investigate the effects of space charge layers in a-Si:H on the conductivity, the thickness dependence of the conductivity is characterized and the conductivities measured at the upper electrodes deposited on a-Si:H are compared with those measured at the lower electrodes deposited on the glass substrate. From our analysis, the bulk conductivity and the thickness of the space charge layer in a-Si:H are characterized quantitatively.