• The KIPS Transactions:PartD
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• v.8D no.5
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• pp.593-604
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• 2001

A database sharing system (DSS) refers to a system for high performance transaction processing. In the DSS, the processing nodes are coupled via a high speed network and share a common database at the disk level. Each node has a local memory and a separate copy of operating system. To reduce the number of disk accesses, the node caches data pages and index pages in its memory buffer. In general, B-tree index pages are accessed more often and thus cached at more processing nodes, than their corresponding data pages. There are also complicated operations in the B-tree such as Fetch, Fetch Next, Insertion and Deletion. Therefore, an efficient cache consistency scheme supporting high level concurrency is required. In this paper, we propose cache consistency schemes using identifiers of index pages and page_LSN of leaf page. The propose schemes can improve the system throughput by reducing the required message traffic between nodes and index re-traversal.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.53-60
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• 2006

Handover of WiBro is based on 802.16e hard handover scheme. When PSS is handover, it is handover that confirm neighbor's cell condition and RAS ID in neighbor advertisement message. Serving RAS transmits HO-notification message to neighbor RAS. Transmiting HO-notification message to neighbor RAS, it occurs many signaling traffics. Also, When WiBro is handover, It occurs many packet loss. Therefore, user suffer service degradation. LPM handover is supporting seamless handover because it buffers data packets during handover. So It is proposed scheme that predicts is LPM handover and reserves target RAS with pre-authentication. These schemes occur many signaling traffics. In this paper, we propose PSS Movement Prediction to solve signaling traffic. Target RAS is decided by old data in history cache. When serving RAS receives HO-notification-RSP message to target RAS, target RAS inform to crossover node. And crossover node bicast data packet. If handover is over, target RAS forward data packet. Therefore, It reduces signaling traffics but increase handover success rate. When history cache success, It decrease about 48% total traffic. But When history cache fails, It increase about 6% total traffic

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.74-76
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• 1998

본 논문에서는 유닉스 파일 시스템에서의 버퍼캐쉬 크기에 따라 사용자 데이터와 메타데이터의 버퍼 캐쉬 히트율을 분석하였다. 그리고 메타 데이터가 유닉스 운영체제 파일 시스템의 성능에 미치는 영향을 분석하고 이를 기반으로 버퍼 캐쉬의 동적 특성과 성능의 장애 요인들을 분석하였다. 유닉스 운영체제에서 사용되는 사용자 데이터와 메타데이터에 대한 버퍼 캐쉬의 동적인 동작을 분석하기 위하여 trace-driven방법을 이용하였으며 이를 위하여 시뮬레이터를 작성.사용하였다. 파일 시스템은 특정 유닉스 버전에 영향을 받지 않기 위해 USF[1]에 기초하였고, 작업부하(workload)로는 Sprite- trace 데이터 중 allspice 서버에서 추출한 데이터를 사용하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.1039-1042
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• 2003

웹 정보의 급격한 양적 팽창은 네트워크 병목 현상과 사용자의 지연시간 증가 및 웹 서버의 과부하 등의 문제를 야기하고 있다. 이를 완화시키기 위한 방법으로 웹 캐슁이 이용되는데, 전통적인 캐슁과는 달리 문서의 종류와 크기가 가변적이며 많은 사용자의 요구를 처리해야하는 특성이 있다. 따라서 본 논문에서는 동적인 웹 환경과 한정된 크기의 웹 캐쉬 공간의 사용 효율을 향상시켜 캐쉬 적중률을 증가시키기 위한 방법으로, 서비스되는 각 파일의 메타정보를 Main Server의 캐쉬에 리스트 형태로 유지하는 CRBM(Client Request Buffer Manager)을 제안한다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.345-348
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• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.421-423
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• 2002

동영상 정보 검색 시스템은 비교적 작은 크기의 동영상 클립과 클립을 인덱싱하기 위한 키 프레임으로 구성된다. 본 논문에서는 동영상 정보 검색 시스템을 위한 버퍼 캐시에서 버퍼 교체 기법을 연구하였고, 버퍼 캐시 사용의 효율성을 연구하였다. 실험을 통해 버퍼 캐시가 좋은 성능을 가지려면 적은 수의 동영상 클립에 요청이 편중되어야 함을 알 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.377-384
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• 2017

The scope of the matrix application is so broad that it can not be limited. A typical matrix application area in computer science is image processing. Particularly, radar scanning equipment implemented on a small embedded system requires real-time matrix transposition for image processing, and since its memory size is small, a general matrix transposition algorithm can not be applied. In this case, matrix transposition must be done in disk space, such as flash disk, using a limited memory buffer. In this paper, we analyze and improve a recently published flash disk-based matrix transposition algorithm named as asymmetric sub-matrix transposition algorithm. The performance analysis shows that the asymmetric sub-matrix transposition algorithm has lower performance than the conventional sub-matrix transposition algorithm, but the improved asymmetric sub-matrix transposition algorithm is superior to the sub-matrix transposition algorithm in 13 of the 16 experimental data.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.