• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.347-356
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• 2009

Precise branch prediction is a critical factor in the IPC Improvement of modern microprocessor architectures. In addition to the branch prediction accuracy, branch prediction delay have a profound impact on overall system performance as well. However, it tends to be overlooked when the architects design the branch predictor. To tolerate branch prediction delay, this paper proposes Early Start Prediction (ESP) technique. The proposed solution dynamically identifies the start instruction of basic block, called as Basic Block Start Address (BB_SA), and the solution uses BB_SA when predicting the branch direction, instead of branch instruction address itself. The performance of the proposed scheme can be further improved by combining short interval hiding technique between BB_SA and branch instruction. The simulation result shows that the proposed solution hides prediction latency, with providing same level of prediction accuracy compared to the conventional predictors. Furthermore, the combination with short interval hiding technique provides a substantial IPC improvement of up to 10.1%, and the IPC is actually same with ideal branch predictor, regardless of branch predictor configurations, such as clock frequency, delay model, and PHT size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1734-1737
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• 2019

This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is also reduced by using the modified gshare predictor with a long history register folding scheme. The aliasing rate decreased to 44.1% and the miss prediction rate decreased to 19.06% on average compared with the gshare branch predictor, one of the most popular two-level branch predictors. Moreover, Compared with the gshare, an average improvement of 1.28% instructions per cycle (IPC) was achieved. Thus, with regard to the accuracy of branch prediction, the HDBP is remarkably useful in boosting the overall performance of the superscalar processor.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.497-502
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• 2002

Conditional branches can severely limit the performance of instruction level parallelism by causing branch penalties. 2-level adaptive branch predictors were developed to get accurate branch prediction in high performance superscalar processors. Although 2 level adaptive branch predictors achieve very high prediction accuracy, they tend to be very costly. In this paper, set-associative cached correlated 2-level branch predictors are proposed to overcome the cost problem in conventional 2-level adaptive branch predictors. According to simulation results, cached correlated predictors deliver higher prediction accuracy than conventional predictors at a significantly lower cost. The best misprediction rates of global and local cached correlated predictors using set-associative caches are 5.99% and 6.28% respectively. They achieve 54% and 17% improvements over those of the conventional 2-level adaptive branch predictors.

• Journal of Practical Agriculture & Fisheries Research
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• v.13 no.1
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• pp.3-17
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• 2011

Pipelines of processor have been growing deeper and issue widths wider over the years. If this trend continues, branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modem processors for FAFF(Food, Agriculture, Forestry, Fisheries)Information Processing. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch PC. Banks 1,2,3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13, up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.10-17
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• 2013

This thesis proposes an automatic embedded core generator system that supports branch prediction. The proposed system includes a dynamic branch prediction module that enhances execution speed of target applications by inserting history/direction flags into BTAC(Branch Target Address Cache). Entries of BHT(Branch History Table) and BTAC are determined based on branch informations extracted by simulation. To verify the effectiveness of the proposed branch prediction module, ARM9TDMI core including a dynamic branch predictor was described in SMDL and generated. Experimental results show that as the number of entry rises, area increase up to 60% while application execution cycle and BTAC miss rate drop by an average of 1.7% and 9.6%, respectively.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.1-10
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• 2009

Precise branch predictor has a profound impact on system performance in modern processor architectures. Recent works show that prediction latency as well as prediction accuracy has a critical impact on overall system performance as well. However, prediction latency tends to be overlooked. In this paper, we propose Branch Pre-Prediction policy to tolerate branch prediction latency. The proposed solution allows that branch predictor can proceed its prediction without any information from the fetch engine, separating the prediction engine from fetch stage. In addition, we propose newly modified BTE structure to support our solution. The simulation result shows that proposed solution can hide most prediction latency with still providing the same level of prediction accuracy. Furthermore, the proposed solution shows even better performance than the ideal case, that is the predictor which always takes a single cycle prediction latency. In our experiments, IPC improvement is up to 11.92% and 5.15% in average, compared to conventional predictor system.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.19-30
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• 2008

Branch history is one of major input vectors in branch prediction. Therefore, the Proper use of branch history plays a critical role of improving branch prediction accuracy. To improve branch prediction accuracy, this paper proposes a new branch history management policy, based on interrelationship analysis of instructions. First of all, we propose three different algorithms to analyze the relationship: register-writhing method, branch-reading method, and merged method. Then we additionally propose variable input gshare predictor as an implementation of these algorithms. In simulation part, we provide performance differences among the algorithms and analyze their characteristics. In addition, we compare branch prediction accuracy between our proposals and conventional fixed input predictors. The performance comparison for optimal input branch predictor is also provided.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1083-1086
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• 2005

Modern superscalar processors exploit Instruction Level Parallelism to achieve high performance by speculative techniques such as branch prediction. The indirect branch target prediction is very difficult compared to the prediction of direct branch target and branch direction, since it has dynamically polymorphic target. We present a accurate and hardware-efficient indirect branch target predictor. It can reduce the tags which has to be stored in the Indirect Branch Target Cache without a sacrifice of the prediction accuracy. We implement the proposed scheme on SimpleScalar and show the efficiency running SPEC95 benchmarks.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.17-28
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• 1999

Recently studies have shown that conditional branches can be accurately predicted by recording the path leading up to the branch. But path predictors are more complex and uncompatible with existing pattern branch predictors. In order to solve these problems, we propose a simple path branch predictor(SPBP) that hashes together two most recent branch instruction addresses. In addition, we propose a pattern/path hybrid branch predictor composed of the SPBP and existing pattern branch predictors. Through the trace-driven simulation of six benchmark programs, the performance improvement by the proposed pattern/path hybrid branch prediction is analysed and validated. The proposed predictor can improve the prediction accuracy from 94.21% to 95.03%.