• Proceedings of the KAIS Fall Conference
• /
• 2006.05a
• /
• pp.209-213
• /
• 2006

In this paper describes image enhancement technique using deconvolution processing for ultrasonic nondestructive testing. . When flaws are detected for B-scan or C-scan, blurring effect which is caused by the moving intervals of transducer degrades the quality of images. In addition, acquisited images suffer form speckle noise which is caused by the ultrasonic components reflected from the grain boundary of material [1,2]. The deconvolution technique can restore sharp peak value or clean image from blurring signal or image. This processing is applied to C-scan image obtained from known specimen. Experimental results show that the deconvolution processing contributes to get improved the quality of C-scan images.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.329-332
• /
• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.10
• /
• pp.728-734
• /
• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• Proceedings of the Korean Information Science Society Conference
• /
• 1998.10c
• /
• pp.662-664
• /
• 1998

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 Update_DR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2log(N+2)의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2756-2758
• /
• 2003

ARM CORE용 칩으로 철도 종합 제어 부분에 이용될 수 있는 main processor 부분을 설계하고, JTAG 기술을 이용하여 그 안정성과 틸팅 기술에 이용될 수 있는 process를 사전 단계에서 bebugging 해보고, 이에 따른 신호 및 성능을 JTAG(Boundary Scan)을 이용하여 시스템의 신호와 파형을 시험 평가한다. 또한 예비 단계로의 JTAG 검증 가능성 여부를 알아보고자 한다. 철도 종합 제어 시스템의 신호 및 정확성을 측정해 보기 위한 선행 연구라 할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.61-68
• /
• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Corrosion Science and Technology
• /
• v.19 no.1
• /
• pp.37-42
• /
• 2020

Even though 304 low-carbon (304L) stainless steel was developed to enhance the resistance to intergranular corrosion and stress corrosion cracking, it is occasionally subject to degradation in harsh environments. The degree of sensitization (DOS) of 304L stainless steel was studied as a function of sensitization using a double-loop electrochemical potentiokinetic reactivation (DL-EPR) method. Sensitizing heat treatment was performed in an Ar atmosphere at 500℃, 600℃, and 700℃, with heat treatment times varying from 0 to 96 h. DOS was measured by the ratio of the peak current density value of the forward scan to that of the reverse scan. After the EPR experiment, the specimen surface was observed by scanning electron microscopy and energy dispersive spectroscopy. The DOS of the specimens heat-treated at 600℃ increased with heat treatment times up to 48 h and then decreased due to a self healing effect. The DOS was higher in specimens heat-treated at 600℃ than those at 500℃ or 700℃. Corrosion of the sensitized specimens occurred mainly at the δ-γ phase boundary. The corrosion morphology at the δ-γ phase boundary changed with sensitizing heat-treatment conditions due to differences in chromium activity in γ austenite and δ ferrite.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.37-44
• /
• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.1
• /
• pp.51-58
• /
• 2016

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.2
• /
• pp.245-249
• /
• 2007

In this paper describes image enhancement technique using deconvolution processing for ultrasonic nondestructive testing. When flaws are detected fur B-scan or C-scan, blurring effect which is caused by the moving intervals of transducer degrades the quality of images. In addition, acquisited images suffer form speckle noise which is caused by the ultrasonic components reflected from the grain boundary of material (1,2). The deconvolution technique can restore sharp peak value or clean image from blurring signal or image. This processing is applied to C-scan image obtained from known specimen. Experimental results show that the deconvolution processing contributes to get improved the quality of C-scan images.