• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• 전력전자학회논문지
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• 제25권2호
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• pp.87-93
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• 2020

This study proposes a gate driver that operates semiconductor switches in the bipolar pulsed power modulator. The proposed gate driver was designed to receive isolated power and synchronized signals through the gate transformer. The gate circuit has a separate delay in the on-and-off operation to prevent a short circuit between the top and bottom switches of each leg. On the basis of the proposed gate circuit, a bipolar pulsed power modulator prototype with a 2.5 kV/100 A rating was developed. Finally, the bipolar pulsed power modulator was tested under resistive load and plasma reactor load conditions. It is verified that the proposed gate driver can be applied to a bipolar pulsed power modulator.

• 한국농공학회논문집
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• 제46권2호
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• pp.41-47
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• 2004

A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1:25 is made of acryl panel dimensioned 0.66 m in width, 0.5 m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. In the flow from the gate inside to the gate outside, the amplitudes of the vibration are measured under the different gate opening and downstream water level conditions. Also revised gate models with 20 mm bottom width are tested under the different gate openings and water levels. The results are analyzed to study the characteristics of the Tainter gate vibration in the sea ward flow. These test results are assessed in comparison with the results in the lake ward flow, as a result, presents the dynamic characteristics of the Tainter gate and a basic data for the guide manuals of gate management.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2005년도 학술발표회(1)
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• pp.252-252
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• 2005

• Journal of Information Display
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• 제7권3호
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• pp.27-30
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• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• 한국정보통신학회논문지
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• 제19권6호
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• pp.1399-1404
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널길이와 채널두께의 비에 따른 드레인 유도 장벽 감소 현상의 변화에 대하여 분석하고자한다. 드레인 전압이 소스 측 전위장벽에 영향을 미칠 정도로 단채널을 갖는 MOSFET에서 발생하는 중요한 이차효과인 드레인 유도 장벽 감소는 문턱전압의 이동 등 트랜지스터 특성에 심각한 영향을 미친다. 드레인 유도 장벽 감소현상을 분석하기 위하여 포아송방정식으로부터 급수형태의 전위분포를 유도하였으며 차단전류가 10^-7 A/m일 경우 비대칭 이중게이트 MOSFET의 상단게이트 전압을 문턱전압으로 정의하였다. 비대칭 이중게이트 MOSFET는 단채널 효과를 감소시키면서 채널길이 및 채널두께를 초소형화할 수 있는 장점이 있으므로 본 연구에서는 채널길이와 두께 비에 따라 드레인 유도 장벽 감소를 관찰하였다. 결과적으로 드레인 유도 장벽 감소현상은 단채널에서 크게 나타났으며 하단게이트 전압, 상하단 게이트 산화막 두께 그리고 채널도핑 농도 등에 따라 큰 영향을 받고 있다는 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

• Ocean and Polar Research
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• 제25권4호
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• pp.459-468
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• 2003

Annual variation of water qualities in the Shihwa Lake were observed 18 times from June 1996 to October 2001. We studied at the station of the upper streams and near the water gate of lake. After the flow of the outer seawater through the water gate, the surface salinity in Shihwa Lake increased to the range of 25-30 psu in both stations after October 1998. Due to the declination of the salinity differences between the surface and the bottom water, the pycnocline in which had existed until 1997 has weakened, and made the water column mix vertically. This led to the improvement of anoxic/hypoxic environment at bottom waters after April 1998. However, despite the continuous flow of the outer seawater, the concentrations of chlorophyll-a at surface layer were varied from $2{\mu}g/l\;to\;60{\mu}g/l$, and these values indicated the eutrophication. The following organic matter load was greatly influencing the surface layer's COD concentration. During the rainy season, the salinity at the surface layer to the below 15 psu resulting in stratification between the surface and bottom layer. Organic matters that were provided from the surface layer to the bottom layer due to active primary production in the year exhausted dissolved oxygen at the bottom layer, and the bulks of organic matters at bottom gave rise to hypoxic or anoxic environment. It was observed that the enrichment of ammonia and phosphate were main factors to worsen the water quality of the Shihwa Lake. The results of examining the annual variations in Shiwha Lake through principal component analysis shown that water characteristics in the rainy season were similar with those before input of outer sea water.

• 전기전자학회논문지
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• 제16권4호
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• pp.283-289
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• 2012

이 논문에서 Trench Power MOSFET의 스위칭 성능을 향상시키기 위한 Separate Gate Technique(SGT)을 제안하였다. Trench Power MOSFET의 스위칭 성능을 개선시키기 위해서는 낮은 gate-to-drain 전하 (Miller 전하)가 요구된다. 이를 위하여 제안된 separate gate technique은 얇은(~500A)의 poly-si을 deposition하여 sidewall을 형성함으로서, 기존의 Trench MOSFET에 비해 얇은 gate를 형성하였다. 이 효과로 gate와 drain에 overlap 되는 면적을 줄일 수 있어 gate bottom에 쌓이는 Qgd를 감소시키는 효과를 얻었고, 이에 따른 전기적인 특성을 Silvaco T-CAD silmulation tool을 이용하여 일반적인 Trench MOSFET과 성능을 비교하였다. 그 결과 Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) 및 Crss(reverse recovery capacitance : Cgd) 모두 개선되었으며, 각각 14.3%, 23%, 30%의 capacitance 감소 효과를 확인하였다. 또한 inverter circuit을 구성하여, Qgd와 capacitance 감소로 인한 24%의 reverse recovery time의 성능향상을 확인하였다. 또한 제안된 소자는 기존 소자와 비교하여 어떠한 전기적 특성저하 없이 공정이 가능하다.