• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.399-405
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• 2018

We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.41-41
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• 2009

We utilized atomic layer deposition (ALD) for the growth of the ZnO channel layers in the oxide thin-film-transistors (TFTs) with a bottom-gate structure using a $SiO_2/p-Si$ substrate. For fundamental study, the effect of the channel thickness and thermal treatment on the TFT performance was investigated. The growth modes for the ALD grown ZnO layer changed from island growth to layer-by-layer growth at thicknesses of > 7.5 nm with highly resistive properties. A channel thickness of 17 nm resulted in the good TFT behavior with an onloff current ratio of > $10^6$ and a field effect mobility of 2.9 without the need for thermal annealing. However, further increases in the channel thickness resulted in a deterioration of the TFT performance or no saturation. The ALD grown ZnO layers showed reduced electrical resistivity and carrier density after thermal treatment in oxygen.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.209.2-209.2
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• 2015

Two dimensional layered materials, such as transition metal dichalcogenides (TMDs) family have been attracted significant attention due to novel physical and chemical properties. Among them, molybdenum disulfide ($MoS_2$) has novel physical phenomena such as absence of dangling bonds, lack of inversion symmetry, valley degrees of freedom. Previous studies have shown that the interface of metal/$MoS_2$ contacts significantly affects device performance due to presence of a scalable Schottky barrier height at their interface, resulting voltage drops and restricting carrier injection. In this study, we report a new device structure by using few-layer graphene as the bottom interconnections, in order to offer Schottky barrier free contact to bi-layer $MoS_2$. The fabrication of process start with mechanically exfoliates bulk graphite that served as the source/drain electrodes. The semiconducting $MoS_2$ flake was deposited onto a $SiO_2$ (280 nm-thick)/Si substrate in which graphene electrodes were pre-deposited. To evaluate the barrier height of contact, we employed thermionic-emission theory to describe our experimental findings. We demonstrate that, the Schottky barrier height dramatically decreases from 300 to 0 meV as function of gate voltages, and further becomes negative values. Our findings suggested that, few-layer graphene could be able to realize ohmic contact and to provide new opportunities in ohmic formations.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.497-497
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• 2013

Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.163-168
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• 2014

Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.813-815
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• 2008

We prepared highly transparent and conductive Oxide/Metal/Oxide(OMO) multilayer by sputtering and developed wet etching process of OMO with a clear edge shape for the first time. The transmittance and sheet-resistance of the OMO are about 89% and $3.3\;{\Omega}/sq.$, respectively. We adopted OMO as a gate electrode of transparent TFT (TTFT) array and integrated OLED on top of the TTFT to result in high aperture ratio of bottom emission AM-OLED.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1564-1567
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• 2005

Zinc oxide thin films were grown at the t emperature of $100^{\circ}C$ and $150^{\circ}C$ by means of plasma enhanced atomic layer deposition (PEALD) and conventional atomic layer deposition for applying to the transparent thin film transistor (TTFT). The growth rate of $1.9{\AA}/cycle$ with oxygen plasma is similar to that of film grown with water. While the sheet resistivity of ZnO grown with water is 1233 ohm/sq, that of film grown with oxygen plasma was too high to measure with 4 point probe and hall measurement system. The resistivity of the films grown with oxygen plasma estimated to be $10^6$ times larger than that of the films grown with water. The difference of electrical property between two films was caused by the O/Zn atomic ratio. We fabricated ZnO-TFT by means of ALD for the first time and the ZnO channel fabricated with water showed saturation mobility of $0.398cm^2/V{\cdot}s$ with bottom gate configuration.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.8
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• pp.50-55
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• 2020

This study investigates the injection molding of a plastic rack gear and focuses on deflections in the part. The causes of deflections were found and resolved through a trade-off study by injection molding analysis. Based on a warpage analysis, the fiber orientation was found to be a dominant factor in the occurrence of deflections. Changes in the part design and various injection conditions were analyzed for their effects in reducing deflections. Based on the trade-off study, a new part bottom design, injection time, and melt temperature were recommended. A trial injection was done for the new plastic rack gear, and measurements showed that its flatness surpassed that of the original part and met the specified requirement. The short injection time, low melt temperature, and symmetric similar configuration of the part contributed to the reduction in deflections. Therefore, optimized gate design and injection conditions as well as a new part design were validated through injection molding analysis in this study.