• 한국산학기술학회논문지
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• 제18권4호
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• pp.175-182
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• 2017

본 와이어 본딩은 발광 다이오드의 패키징 공정에서 매우 중요한 공정으로 금 와이어를 이용하여 발광 다이오드 칩과 리드 프레임을 연결함으로써 다음 공정에서의 전기적 작동을 가능하게 한다. 와이어 본딩 공정은 얇은 금속선을 연결하는 공정으로 열 압착 본딩(thermo compression bonding)과 초음파 본딩(ultra sonic bonding)이 있다. 일반적인 와이어 본딩 공정은 LED 칩 상부 전극 부위에 볼 모양의 본딩을 진행하는 1st ball bonding 공정, loop를 형성하여 다른 전원 연결부위로 wire를 늘어뜨리는 looping 공정, 다른 전극 부위 상부에 stitch를 형성하여 bonding 하는 2nd stitch bonding으로 구분된다. 본 논문에서는 발광 다이오드 다이 본딩 공정에 영향을 주는 다양한 공정 변수에 대하여 분석을 수행하였다. 그리고 반응 표면 분석법을 통하여 Zener 다이오드 칩과 PLCC 발광 다이오드 패키지 프레임을 연결하는 공정 최적화 결과를 도출하였다. 실험 계획법은 5인자, 3수준에 대하여 설정하였으며 4가지 반응에 대하여 인자를 분석하였다. 결과적으로 본 연구에서는 모든 목표에 맞는 최적 조건을 도출하였다.

• 마이크로전자및패키징학회지
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• 제28권2호
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• pp.65-70
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• 2021

본 연구에서는 레이저 접합 공정을 이용하여 flame retardant-4 (FR-4) 인쇄회로기판 (printed circuit board, PCB)의 organic solderability preservative (OSP) 표면처리 된 Cu pad와 전자부품을 Sn-57Bi-1Ag 저온 솔더 페이스트로 접합을 한 후 접합부의 계면 특성과 기계적 특성에 대하여 보고 하였다. 레이저 접합 공정은 레이저 파워 및 시간 등을 다르게 진행하여 접합 공정 조건이 접합부의 계면 및 기계적 특성에 미치는 영향을 살펴보았다. 레이저 접합 공정의 산업적 적용을 위하여 산업적으로 많이 이용되고 있는 리플로우 접합 공정을 이용한 접합부의 특성과도 비교 하였다. 레이저 접합 공정 적용 결과 2, 3 s의 짧은 공정 시간에도 계면에 Cu₆Sn₅ 금속간화합물 (intermetallic compound, IMC)를 생성하여 접합부를 안정적으로 형성함을 확인 하였다. 또한, 리플로우 공정과 비교해 보았을 때 레이저 접합 공정을 적용할 경우 접합부의 보이드 형성이 억제됨을 확인할 수 있었으며 접합부의 전단강도도 리플로우 공정 접합부보다 높은 기계적 강도를 나타냈다. 따라서, 레이저 접합 공정을 적용할 경우 짧은 접합 공정 시간에도 불구하고 안정적인 접합부 형성 및 높은 기계적 강도를 확보할 수 있는 것으로 기대된다.

• ETRI Journal
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• 제35권6호
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.204-207
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• 2003

The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet to tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of sample was conducted. A TiW/Cu UBM structure was adopted and sample was aging treated to analyze the effect of intermetallic compound with time variation. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the fine joint area was observed by using SEM, TEM and EDS. In result, the shear strength was decreased of about 20% in the $100{\mu}m$ sample at $170^{\circ}C$ aging compared with the maximum shear strength of same pad size sample. In the case of the $120^{\circ}C$ aging treatment, 17% of decrease in shear strength was measured at the $100{\mu}m$ pad size sample. Also, intremetallic compound of $Cu_6Sn_5$ and $Cu_3Sn$ were observed through the TEM measurement by using an FIB technique that is very useful to prepare TEM thin foil specimens from the solder joint interface.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.7-11
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• 2013

As thermosonic ball bonding is developed for more and more advanced applications in the electronic packaging industry, the control of process stresses induced on the integrated circuits becomes more important. If Cu bonding wire is used instead of Au wire, larger ultrasonic levels are common during bonding. For advanced microchips the use of Cu based wire is risky because the ultrasonic stresses can cause chip damage. This risk needs to be managed by e.g. the use of ultrasound during the impact stage of the ball on the pad ("pre-bleed") as it can reduce the strain hardening effect, which leads to a softer deformed ball that can be bonded with less ultrasound. To find the best profiles of ultrasound during impact, a numerical model is reported for ultrasonic bonding with capillary dynamics combined with a geometrical model describing ball deformation based on volume conservation and stress balance. This leads to an efficient procedure of ball bond modelling bypassing plasticity and contact pairs. The ultrasonic force and average stress at the bond zone are extracted from the numerical experiments for a $50{\mu}m$ diameter free air ball deformed by a capillary with a hole diameter of $35{\mu}m$ at the tip, a chamfer diameter of $51{\mu}m$, a chamfer angle of $90^{\circ}$, and a face angle of $1^{\circ}$. An upper limit of the ultrasonic amplitude during impact is derived below which the ultrasonic shear stress at the interface is not higher than 120 MPa, which can be recommended for low stress bonding.

• 한국정밀공학회지
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• 제22권7호
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• pp.137-145
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• 2005

A new design of contact detection algorithm is proposed for the z-axis of a wire bonder that interconnects between pads and leads in semiconductor manufacturing processes. Fast and stable contact detection of the z-axis is extremely important fer maintaining proper quality in the fine pitch gold wire bonding process, which has a small pad size of below 70um. The new method is based on a statistical approach and designed for the discrete Kalman filter. Real wire bonding experimental results are presented to demonstrate the advantages of the proposed algorithm.

• Journal of Welding and Joining
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• 제22권3호
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• pp.62-68
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• 2004

The strip Au bumps are bonded using longitudinal ultrasonic far the electronic package. Au bumps on the chip and substrate are aligned in a crossed shape, and the ultrasonic is imposed on the chip to form the solid-state bond between the Au bumps. Deformed bump shapes are calculated using the finite element method, and the bond strength is measured experimentally. The crossed strip Au bumps are deformed similar to the saddle, which provides larger contact surface area and higher friction force. Compared with the previous bonding method between the Au bump and planar pad, higher bond strength is obtained using the crossed strip bumps.

• ETRI Journal
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• 제37권3호
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• pp.523-532
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• 2015

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.76-81
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• 2011

본 논문에서는 비아 절단 구조를 제안하고 2층 구조의 DRAM 패키지 기판 설계에 적용하여 낮은 임피던스를 가지는 파워 분배망(Power Distribution Network)을 구현하였다. 제안한 신규 비아 구조는 비아의 일부가 절단된 형태이고 본딩 패드와 결합하여 넓은 배선 면적을 필요로 하지 않는 장점을 가진다. 또한 비아 절단 구조를 적용한 설계에서는 본딩 패드에서 VSSQ까지의 배선 경로를 효과적으로 단축시킴으로써 PDN 임피던스를 개선시킬 수 있다. DRAM 패키지 기판 상의 윈도우 영역 형성과 동시에 비아의 일부 영역이 제거되므로 비아 절단 구조 제작을 위한 추가적인 공정은 없다. 또한 비아 홀 내부를 솔더 레지스트로 채움으로써 버(Burr) 발생을 최소화하였으며, 이를 패키지 기판 단면 촬영을 통해 검증하였다. 비아 절단 구조의 적용 및 VDDQ/VSSQ 배치에 의한 PDN 임피던스 변화를 검증하기 위해서 3차원 전자장 시뮬레이션 및 네트워크 분석기 측정을 통해 기존 방식을 적용한 패키지 기판과 비교 검증을 진행하였다. 신규 DRAM 패키지 기판은 대부분의 주파수 범위에서 보다 우수한 PDN 임피던스를 가졌으며, 이는 제안한 비아 절단 구조와 파워/그라운드 설계 배치가 PDN 임피던스 감소에 효과적임을 증명한다.