• Title/Summary/Keyword: block-adaptive

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Dual BTC Image Coding technique for Full HD Display Driver (Full HD 디스플레이 드라이버를 위한 Dual BTC 영상부호화 기법)

  • Kim, Jin-Hyung;Ko, Yun-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.49 no.4
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    • pp.1-9
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    • 2012
  • LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.

Low-Complexity H.264/AVC Deblocking Filter based on Variable Block Sizes (가변블록 기반 저복잡도 H.264/AVC 디블록킹 필터)

  • Shin, Seung-Ho;Doh, Nam-Keum;Kim, Tae-Yong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.4
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    • pp.41-49
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    • 2008
  • H.264/AVC supports variable block motion compensation, multiple reference images, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with the existing compression technologies. While these coding technologies are major functions of compression rate improvement, they lead to high complexity at the same time. For the H.264 video coding technology to be actually applied on low-end / low-bit rates terminals more extensively, it is essential to improve tile coding speed. Currently the deblocking filter that can improve the moving picture's subjective image quality to a certain degree is used on low-end terminals to a limited extent due to computational complexity. In this paper, a performance improvement method of the deblocking filter that efficiently reduces the blocking artifacts occurred during the compression of low-bit rates digital motion pictures is suggested. In the method proposed in this paper, the image's spatial correlational characteristics are extracted by using the variable block information of motion compensation; the filtering is divided into 4 modes according to the characteristics, and adaptive filtering is executed in the divided regions. The proposed deblocking method reduces the blocking artifacts, prevents excessive blurring effects, and improves the performance about $30{\sim}40%$ compared with the existing method.

Design of video encoder using Multi-dimensional DCT (다차원 DCT를 이용한 비디오 부호화기 설계)

  • Jeon, S.Y.;Choi, W.J.;Oh, S.J.;Jeong, S.Y.;Choi, J.S.;Moon, K.A.;Hong, J.W.;Ahn, C.B.
    • Journal of Broadcast Engineering
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    • v.13 no.5
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    • pp.732-743
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    • 2008
  • In H.264/AVC, 4$\times$4 block transform is used for intra and inter prediction instead of 8$\times$8 block transform. Using small block size coding, H.264/AVC obtains high temporal prediction efficiency, however, it has limitation in utilizing spatial redundancy. Motivated on these points, we propose a multi-dimensional transform which achieves both the accuracy of temporal prediction as well as effective use of spatial redundancy. From preliminary experiments, the proposed multi-dimensional transform achieves higher energy compaction than 2-D DCT used in H.264. We designed an integer-based transform and quantization coder for multi-dimensional coder. Moreover, several additional methods for multi-dimensional coder are proposed, which are cube forming, scan order, mode decision and updating parameters. The Context-based Adaptive Variable-Length Coding (CAVLC) used in H.264 was employed for the entropy coder. Simulation results show that the performance of the multi-dimensional codec appears similar to that of H.264 in lower bit rates although the rate-distortion curves of the multi-dimensional DCT measured by entropy and the number of non-zero coefficients show remarkably higher performance than those of H.264/AVC. This implies that more efficient entropy coder optimized to the statistics of multi-dimensional DCT coefficients and rate-distortion operation are needed to take full advantage of the multi-dimensional DCT. There remains many issues and future works about multi-dimensional coder to improve coding efficiency over H.264/AVC.

Design of Low Power Optical Channel for DisplayPort Interface (저전력 광채널용 디스플레이포트 인터페이스 설계)

  • Seo, Jun-Hyup;Park, In-Hang;Jang, Hae-Jong;Bae, Gi-Yeol;Kang, Jin-Ku
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.58-63
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    • 2013
  • This paper presents a transceiver design for DisplayPort interface using an optical channel. By converting the electronic channel to the optical channel, the DisplayPort's main channel can provide a high-speed data transmission for long distance. The design converting the electronic channel to the optical channel in the main channel and AUX channel of the DisplayPort is presented in this paper. Futhermore, the HPD signal transmission by using AUX channel is proposed. In order to minimize power consumption, this paper also proposed a method of controlling the TX block in the main link. The proposed system is designed by a FPGA and an optical module. The FPGA used 651 ALUT(adaptive look-up table)s, 511 resisters and 324 block memory bits. The maximum operating rate of the FPGA is 250MHz. With the proposed power control scheme, 740mW of power dissipation reduction can be achieved at the main link optical TX module.

Classified Image Compression and Coding using Multi-Layer Percetpron (다층구조 퍼셉트론을 이용한 분류 영상압축 및 코딩)

  • 조광보;박철훈;이수영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.11
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    • pp.2264-2275
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    • 1994
  • In this paper, image compression based on neural networks is presented with block classification and coding. Multilayer neural networks with error back-propagation learning algorithm are used to transform the normalized image date into the compressed hidden values by reducing spatial redundancies. Image compression can basically be achieved with smaller number of hidden neurons than the numbers of input and output neurons. Additionally, the image blocks can be grouped for adaptive compression rates depending on the characteristics of the complexity of the blocks in accordance with the sensitivity of the human visual system(HVS). The quantized output of the hidden neuron can also be entropy coded for an efficient transmission. In computer simulation, this approach lie in the good performances even with images outside the training set and about 25:1 compression rate was achieved using the entropy coding without much degradation of the reconstructed images.

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High Efficient Entropy Coding For Edge Image Compression

  • Han, Jong-Woo;Kim, Do-Hyun;Kim, Yoon
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.31-40
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    • 2016
  • In this paper, we analyse the characteristics of the edge image and propose a new entropy coding optimized to the compression of the edge image. The pixel values of the edge image have the Gaussian distribution around '0', and most of the pixel values are '0'. By using this analysis, the Zero Block technique is utilized in spatial domain. And the Intra Prediction Mode of the edge image is similar to the mode of the surrounding blocks or likely to be the Planar Mode or the Horizontal Mode. In this paper, we make use of the MPM technique that produces the Intra Prediction Mode with high probability modes. By utilizing the above properties, we design a new entropy coding method that is suitable for edge image and perform the compression. In case the existing compression techniques are applied to edge image, compression ratio is low and the algorithm is complicated as more than necessity and the running time is very long, because those techniques are based on the natural images. However, the compression ratio and the running time of the proposed technique is high and very short, respectively, because the proposed algorithm is optimized to the compression of the edge image. Experimental results indicate that the proposed algorithm provides better visual and PSNR performance up to 11 times than the JPEG.

IPS-Mode Dynamic LCD-TV Realization with Low Black Luminance and High Contrast by Adaptive Dynamic Image Control Technology

  • Oh, E.Y.;Baik, S.H.;Sohn, M.H.;Kim, K.D.;Hong, H.J.;Bang, J.Y.;Kwon, K.J.;Kim, M.H.;Jang, H.;Yoon, J.K.;Chung, I.J.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.799-802
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    • 2004
  • In this paper, the active backlight control technology with data processing algorithm was developed in order to improve image quality for IPS-mode LCD-TV applications. The image blinking problem caused by repeatedly abrupt change of the backlight luminance was solved by algorithms-Fba(Flexible Boundary algorithm) and Cfa(Cumulative Feedback algorithm)-and the optimized number and space of backlight dimming steps based on perception. In the IPS-mode 42" TFT-LCD panel, the dynamic contrast ratio can be more than twice the typical level by means of lower block luminance and higher white luminance. Additionally, Power consumption and LCD temperature was decreased.

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Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

  • Park, Kwang-Hee;Yang, Jun-Sik;Chang, Joon-Hyuk;Kim, Deok-Hwan
    • ETRI Journal
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    • v.30 no.6
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    • pp.790-798
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    • 2008
  • Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

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Recursive Estimation of Biased Zero-Error Probability for Adaptive Systems under Non-Gaussian Noise (비-가우시안 잡음하의 적응 시스템을 위한 바이어스된 영-오차확률의 반복적 추정법)

  • Kim, Namyong
    • Journal of Internet Computing and Services
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    • v.17 no.1
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    • pp.1-6
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    • 2016
  • The biased zero-error probability and its related algorithms require heavy computational burden related with some summation operations at each iteration time. In this paper, a recursive approach to the biased zero-error probability and related algorithms are proposed, and compared in the simulation environment of shallow water communication channels with ambient noise of biased Gaussian and impulsive noise. The proposed recursive method has significantly reduced computational burden regardless of sample size, contrast to the original MBZEP algorithm with computational complexity proportional to sample size. With this computational efficiency the proposed algorithm, compared with the block-processing method, shows the equivalent robustness to multipath fading, biased Gaussian and impulsive noise.

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

  • Ishihara, Shota;Xia, Zhengfan;Hariyama, Masanori;Kameyama, Michitaka
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.165-175
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    • 2010
  • This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.