• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.81-88
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• 2004

Turbo code has been adopted in the 3GPP standard, since its performance is very close to the Shannon limit. However, the turbo decoder requires a lot of computations and the amount of the memory increases as the block size of turbo codes becomes larger. In order to reduce the complexity of the turbo decoder, the Log-MAP, the Max-Log-MAP and the sliding window algorithm have been proposed. In this paper, the performance of turbo codes adopted in the 3GPP standard is analyzed by using the floating point and the fixed point implementation. The efficient decoding method is also proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.255-257
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• 2011

본 논문에서는 지상파 3D HDTV 방송 서비스를 제공하기 위하여 기존의 유럽형 HDTV 방송 서비스인 DVB-T2 전송 시스템의 채널 부호군 중 외부부호로 쓰이는 BCH 부호를 연판정 복호가 가능한 Block Turbo Code로 대체함으로써 생기는 성능 이득과 높은 부호율을 달성하기 위한 방법을 제안하였다. 기존의 DVB-T2 시스템에서 외부부호로 쓰이는 BCH 부호의 부호율의 경우 0.994정도의 높은 부호율을 가진다. 따라서 이에 준하는 높은 부호율을 가지면서 연판정 복호가 가능한 BTC 부호를 제안하고, 기존의 BTC 보다 더 높은 부호율을 가지는 BTC 부호를 설계한다. 모의 실험을 통하여 새롭게 제안된 BTC 에서도 반복복호의 이득이 생기는 것을 확인하고 기존 DVB-T2 시스템의 BCH 부호보다 성능이 우수함을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1613-1619
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• 2004

Turbo codes of long block sizes have been known to show very good performance in an AWGN channel and the turbo code has been strongly recommended as error correction code for W-CDMA in 3GPP(3rd Generation Partnership Project). Recently, turbo codes of short block sizes suitable for real time communication systems have attracted a lot of attention. Thus, in this paper we consider the turbo code of 1/3 code rate and short frame size of 192 bits in ITU-R channel model. We analyzed the performance of W-CDMA systems of 10MHz bandwidths employing RAKE receiver with not only MRC diversity but also SOVA-based turbo code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.86-95
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• 2003

With the advent of future mobile communication systems, the wireless transmission of the huge amount of multimedia data over the error-prone multipath fading channel has to overcome the inherent sensitivity to channel errors. To alleviate the effect of the channel errors, hosts of techniques based on the forward error correction(FEC) has been proposed at the cost of overhead rate. Among the FEC techniques, turbo code, whose performance has been shown to be very close to the Shannon limit, can be classified as a block-based error correction code. In this paper, considering the variable packet size of the multimedia data, we analyzed turbo codes employing the variable-sized interleaver. The effect of the various parameters on the BER performance is analyzed. We show that the turbo codes can be used as efficient error correction codes of multimedia data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.215-223
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• 2003

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GFP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, l/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and denveloped the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1046-1051
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• 1999

It is well known that Parallel Concatenated Convolutional Codes(turbo codes) has a good performance for long block sizes. This thesis has analyzed the performance of turbo code which is based on voice or control frames with short frame sizes in the future mobile communication system. Also, at the similar decoding complexity, the performance of turbo code and convolutional codes in the speech/control frames, and the applicability of this system are considered. As a result, turbo code in short frame sizes present the performance of a BER of $10^{-3}$ or more over 3 iterations in the future mobile communication system. However, at a BER of $10^{-3}$ , if the same complexity is considered, the performance of rate 1/2 turbo code with K = 5 is better than that of convolutional code with K = 9 at low $E_b/N_0$, and the performance of turbo code with K = 3 is superior to that of convolutional code with K = 7. Rate 1/3 turbo code with K = 3 and 5 have similar to performance of rate 1/2 turbo code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2C
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• pp.161-166
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• 2008

In the parallel-architecture turbo codes, the constituent interleaver must avoid memory collision. This paper proposes a collision-free interleaver structure composed of a Latin square matrix and pre-designed interleavers. Our proposed interleavers can be easily optimized for various information block sizes and for various degrees of parallelism. Their performances were evaluated by computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.420-425
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• 2012

A forward error correction (FEC) coding techniques is one of time diversity techniques with which the effect of channel impairments due to noise and fading are spreaded over independently, and thus the performance could be improved. Therefore, the performance of the FEC scheme can be maximized if we minimize the correlation of channel information across over a codeword. In this paper, we propose a block turbo code with the maximized time diversity effect which may be reduced due to utilization of high order modulation schemes and due to transmission over a comparatively fast fading environment. Especially, we propose a very simple formula to calculate the address of coded bit allocation, and thus we do not need any additional outer interleavers, i.e., inter-codeword interleavers. The simulation resuts investigated in this paper reveal that the proposed scheme can provide the performance gain of more than a few decibels compared to the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1006-1013
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• 2008

CZZ (Concatenated Zigzag) Code is a class of fast encodable LDPC codes. In the case that LDPC codes including CZZ codes have short length, short cycles seriously affect the code performance. In this paper, we construct CZZ codes using various degree-2 polynomial interleavers which eliminate cycles of length 4 and through simulation, compare the performance of these CZZ codes and turbo codes in many different fading channels. Especially, quasi-static fading channel, block fading channel, uncorrelated fading channel, and correlated fading channel are considered. Since CZZ codes show similar performance as turbo codes, they can be used in the next generation wireless communication systems.