• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.843-850
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• 2004

As mobile devices prevail, requests for various services using mobile devices have increased. Requests for application services that require large data space such as multimedia, game and database [1] specifically have greatly increased. However, mobile appliances have difficulty in applying various services like a wire environment, because the storage capacity of one is not enough. Therefore, research (5) which provides remote storage service for mobile appliances using iSCSI is being conducted to overcome storage space limitations in mobile appliances. But, when iSCSI is applied to mobile appliances, iSCSI I/O performance drops rapidly if a iSCSI client moves from the server to a far away position. In the case of write operation, $28\%$ reduction of I/O performance occurred when the latency of network is 64ms. This is because the iSCSI has a structural quality that is very .sensitive to delay time. In this paper, we will introduce an intermediate target server and localize iSCSI target to improve the shortcomings of iSCSI performance dropping sharply as latency increases when mobile appliances recede from a storage server.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.706-715
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• 2004

In this paper, to decide the watermark embedding positions and embed the watermark we use the subband tee structure which is presented in the wavelet domain and the edge information in the spatial domain. The significant frequency region is estimated by the subband searching from the higher frequency subband to the lower frequency subband. LH1 subband which has the higher frequency in tree structure of the wavelet domain is divided into 4${\times}$4 submatrices, and the threshold which is used in the watermark embedding is obtained by the blockmatrix which is consists by the average of 4${\times}$4 submatrices. Also the watermark embedding position, Keymap is generated by the blockmatrix for the energy distribution in the frequency domain and the edge information in the spatial domain. The watermark is embedded into the wavelet coefficients using the Keymap and the random sequence generated by LFSR(Linear feedback shift register). Finally after the inverse wavelet transform the watermark embedded image is obtained. the proposed watermarking algorithm showed PSNR over 2㏈ and had the higher results from 2％ to 8％ in the comparison with the previous research for the attack such as the JPEG compression and the general image processing just like blurring, sharpening and gaussian noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of Dental Rehabilitation and Applied Science
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• v.25 no.3
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• pp.255-265
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• 2009

Recently many studies have been published on application of immediate loaded implants. However, the immediate loading protocol has not been well documented. The purpose of the present study was to evaluate the stress distribution between bone-implant interfaces and the effect of implant length in the anterior maxilla using 3 dimensional finite element analyses. The diameter 4.0 mm threaded type implants with different length(8.5 mm, 10.0 mm, 11.5 mm, 13.0 mm, 15.0 mm) were used in this study. The bone quality of anterior maxillary bone block was assumed to D3 bone. Bone-implant interfaces of immediately loaded implant were constructed using a contact element for simulating the non osseointegration status. For simplification of all the processing procedures, all of the material assumed to be homogenous, isotropic, and linearly elastic. The 178 N of static force was applied on the middle of the palatoincisal line angle of the abutment with $120^{\circ}$ angle to the long axis of abutment. Maximum von Mises stress were concentrated on the labial cortical bone of the implant neck area, especially at the cortical-cancellous bone interfaces. Compared the different length, highest peak stress value was observed at the 8.5 mm implants and the results indicated a tendency towards favorable stress distribution on the bone, when the length was increased. Presence of cortical bone was very important to immediate loading, and it appears that implants of a length more than 13 mm are preferable for immediate loading at the anterior maxilla.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.2
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• pp.33-41
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• 2001

Currently, the compression is one of the most important technology in multimedia society. Audio files arc rapidly propagated throughout internet Among them, the most famous one is MP-3(MPEC-1 Laver3) which can obtain CD tone from 128Kbps, but tone quality is abruptly down below 64Kbps. MPEC-II AAC(Advanccd Audio Coding) is not compatible with MPEG 1, but it has high compression of 1.4 times than MP 3, has max. 7.1 and 96KHz sampling rate. In this paper, we propose an algorithm that decreased the capacity of AAC encoding computation but increased the processing speed by optimizing psychoacoustic model which has enormous amount of computation in MPEG 2 AAC encoder. The optimized psychoacoustic model algorithm was implemented by C++ language. The experiment shows that the psychoacoustic model carries out FFT(Fast Fourier Transform) computation of 3048 point with 44.1 KHz sampling rate for SMR(Signal to Masking Ratio), and each entropy value is inputted to the subband filters for the control of encoder block. The proposed psychoacoustic model is operated with high speed because of optimization of unpredictable value. Also, when we transform unpredictable value into a tonality index, the speed of operation process is increased by a tonality index optimized in high frequency range.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.286-294
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• 2010

This study was performed to identify the cerebral network associated with sensation through the tickling stimulation, which is distinctive from the rest of other networks processing normal stimulation and to investigate the difference of laughing mechanism which is closely related to tickling using functional MRI(fMRI). A 16 healthy volunteers (mean age: 28.9) on a 3.0T MR scanner during two sensation conditions. Counterbalanced stimulus were presented across the participants, and the stimulation was used block design. Acquired data was analyzed by the statistical parametric mapping (SPM 99). Subject and group analysis was performed. Individual analysis showed the activation of somatic sensation area in both tasks and the tickling sensation test showed more activated area in the Wernicke's area(BA40) compared to the normal sensation. The group analysis result shows that under normal stimulations, both sides of somatosensory cortices(BA 1,2 and 3) were activated and under tickling stimulation, not only the cortices but also those huge activation on thalamus, cingulate gyrus and insular lobe were detected. When the tickling was stopped, significant activations were shown in right cingulate gyrus, left MFG area and left insular lobe. A cerebral area responsible for recognizing tickling sensation was examined and the primitive stimulation such as tickling is much closely related to laugh, which is an important factor for various social activities.

• Asian-Australasian Journal of Animal Sciences
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• v.13 no.5
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• pp.645-652
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• 2000

A total of 80 piglets ($5.18{\pm}0.61kg$ of BW; 16 d of age) were fed experimental diets to evaluate the effect of extruded full-fat soybean (EFS) on the growth of eatly weaned pigs. Pigs were allotted into five treatments based on body weight, in a completely randomized block design. Each treatment has 4 replicates of 4 animals each. Treatments consisted of diets representing substitutional ratios of EFS for soybean meal. 1) 100:0 (SBM), 2) 75:25 (EFS 25), 3) 50:50 (EFS 50), 4) 25:75 (EFS 75) and 5) 0:100 (EFS 100). During phase I (d 0 to 7), piglets were fed diets containing 3,340 kcal ME, 26% crude protein, 1.85% lysine, 1.0% Ca and 0.9% P. For phase II (d 8 to 21), piglets were fed diets supplying 3,340 kcal ME, 23% crude protein, 1.65% lysine, 0.9% Ca and 0.8% P. Urease activity (pH rise) of EFS (0.18) was three times higher than that of SBM (0.06) indicating that processing conditions were not efficient enough to inactivate urease activity. During the first week postweaning, pigs fed SBM had significantly greater average daily gain (ADG), average daily feed intake (ADFI) and better feed conversion ratio (FCR) compared to pigs fed FFS diets. Linear negative effect on growth rate was found as the inclusion rate of FFS increased. During d 8 - 21 postweaning, piglets fed EFS 50 diet showed the best ADG and FCR despite no significant difference between treatment SBM and EFS 25 have been observed. Overall, piglets fed diets up to 50% FFS inclusion rate exhibited similar weight gain. Only piglets fed EFS 100 diet showed a significantly decreased growth rate. No other significant effect was found in feed intake and feed conversion ratio. At d 7, dry matter digestibility was higher in pigs fed SBM diet than piglets fed EFS 75 diet (p<0.05) and crude protein digestibility was higher in piglets fed SBM diet than piglets fed EFS 50, EFS 75 and EFS 100 (p<0.05). At d 21, no difference other than in phosphorus digestibility was detected. This indicates that piglets at 21 d postweaning are capable of utilizing nutrients from FFS. No treatment effects were detected in blood metabolites. The data suggests that piglets at 16 d of age are not sufficiently mature to use extruded FFS in their diets. Nevertheless, FFS seemed to be able to replace upto 50% of SBM in weaned piglet diet.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.