• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.6
• /
• pp.1068-1073
• /
• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1516-1520
• /
• 1987

This paper proposes fault simulation algorithms for Domino CMOS circuits, The inputs having fanouts are described correctly in the algorithms by modeling the functional block in the Domino CMOS circuits as Modified dependency matrix. The proposed algorithms generate easily the test sequence which can detect the s-a-O, s-a-I, stuckopen faults in the Domino CMOS circuits.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.1 s.343
• /
• pp.121-126
• /
• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.6
• /
• pp.673-677
• /
• 2010

Recently, NAND flash memory has been widely used in embedded systems, personal computers, and server systems because of its attractive features, such as non-volatility, fast access speed, shock resistance, and low power consumption. Due to its hardware characteristics, specifically its 'erase-before-write' feature, Flash Translation Layer is required for using flash memory like hard disk drive. Many FTL schemes have been proposed, but conventional FTL schemes have problems such as block thrashing and block associativity problem. The KAST scheme tried to solve these problems by limiting the number of associations between data block and log block to K. But it has also block thrashing problem in random access I/O pattern. In this paper, we proposed a new FTL scheme, UDA-LBAST. Like KAST, the proposed scheme also limits the log block association, but does not limit data block association. So we could minimize the cost of merge operations, and reduce merge costs by using a new block reclaim scheme, log block garbage collection.

• Journal of KIISE
• /
• v.44 no.4
• /
• pp.363-373
• /
• 2017

Ext4 file system is widely used in various computing environments such as those of the PC, the server, and the Linux-based embedded system. Ext4, which uses a buffer for block I/O, provides fsync() system call to applications to guarantee the consistency of a specific file. A log of the analytical studies regarding the operation of Ext4 and the improvement of its performance has been compiled, but it has not been studied in detail in terms of kernel versions. We figure out that the behavior of fsync() system call is different depending on the kernel version. Between the kernel versions of 3.4.0 and 4.7.2, 3.4.0, 3.8.0, and 4.6.2 showed behavioral differences regarding the fsync() system call. The latency of fsync() in kernel 3.4.0 is longer than that of the more-advanced 3.7.10; meanwhile, the characteristics of 3.8.0 enabled the disruption of the Ext4 journaling order, but the ordered defect was solved with 4.6.2.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.5
• /
• pp.333-337
• /
• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• The KIPS Transactions:PartC
• /
• v.11C no.6 s.95
• /
• pp.843-850
• /
• 2004

As mobile devices prevail, requests for various services using mobile devices have increased. Requests for application services that require large data space such as multimedia, game and database [1] specifically have greatly increased. However, mobile appliances have difficulty in applying various services like a wire environment, because the storage capacity of one is not enough. Therefore, research (5) which provides remote storage service for mobile appliances using iSCSI is being conducted to overcome storage space limitations in mobile appliances. But, when iSCSI is applied to mobile appliances, iSCSI I/O performance drops rapidly if a iSCSI client moves from the server to a far away position. In the case of write operation, $28\%$ reduction of I/O performance occurred when the latency of network is 64ms. This is because the iSCSI has a structural quality that is very .sensitive to delay time. In this paper, we will introduce an intermediate target server and localize iSCSI target to improve the shortcomings of iSCSI performance dropping sharply as latency increases when mobile appliances recede from a storage server.

• 제어로봇시스템학회:학술대회논문집
• /
• 1987.10b
• /
• pp.413-418
• /
• 1987

The software developed for the large scale Programmable Controller consists of the programmer's S/W, the Controller's S/W the RBC's (Remote Base Controller's) S/W and the Analog's S/W. The programmer's S/W, running on the Programmer, includes the editor, the compiler, the communication program, and some other programs for easy use. The Controller S/W, which requires the fast scanning time, consists of the BTI( Block Type Instruction) solving program, the timer service routine, the i/o update program, the communication program and etc. The RBC's S/W includes the communication program, the error recovery program and the i/o processing program. The analog S/W, controlled by the Programmer, includes the PID program. The data communication between the Programmer and the Controller the Controller and the RBC, and the RBC and the Analog are developed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.60-66
• /
• 2000

This paper proposes a design of phone card IC with the self-test features and the hardware and software security functions. We design and verify the proposed functions with modeling the terminal system environment. The proposed phone card IC provides instructions and a non-volatile memory block containing the manufacturer / issuer / user information, the unit (money) value, and the security key. The self-test functions are designed to improve the test time degradation due to a serial I/O communication. Also some security features are implemented using hardware and software approaches.

• Journal of The Korean Society of Grassland and Forage Science
• /
• v.16 no.4
• /
• pp.260-266
• /
• 1996

To find out the residual effect of phosphate fertilization level on the dry matter yield and nutrient plloductivity of pasture plants, this experiment was arranged as a randomized complete block design with six treatments(0-0, 50-50, 100-65, 150-65, 200-65 and 250-65kg $P_2O_5$), those were composed of three $P_2O_5$ fertilization level(0,50 and 65kg $P_2O_5$ after phosphate fertilization trial with six treatments(0, 50, 100, 150, 200 and 250kg $P_2O_5$/ha) from 1989 to 1992, and conducted at hilly land in Kwangju, Kyonggi Province from 1993 to 1994. The results obtained are summarized as follows : As the available phosphate of soil increase, the early growth and cover degree of pasture plants wintered were more favorable. With 150-65kg $P_2O_5$ application for two years, the average dry matter yield of grasses, 9,862kglha was similared to that of 200-65kg $P_2O_5$/ha. The crude protein and energy productivity of pasture plants tended to increase as available phosphate of soil was increased, but those were not different between 150-65 and 250-65kg P 2 0 4 a Efficiency of $P_2O_5$ was highest at $P_2O_5$ 150-65kg/ha fertilization, wHich produced dry matter 11 1.8kg. net energy lactation(NEL) 67 1.2M.f per I kg P205. Therefore, phosphate fertilization is recommended strongly application with 150kg/ha for three years after pasture establishment, and then 65kg/ha for two years a reasonabl management in hilly grassland.