• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.338-347
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• 2007

In this paper, a weighted block adaptive channel estimation (WBA-CE) for a space-time block-coded (STBC) single-carrier transmission with a cyclic-prefix is proposed. In operation of the WBA-CE, a STBC matrix-wise block for filter input symbols is first formulated. Applying a weighted a posteriori error vector-based least-square (LS) criterion for this block, the coefficient correction terms of the WBA-CE are then computed. An approximate steady-state excess mean-square error (EMSE) of the WBA-CE for the stationary optimal coefficient is also analyzed. Simulation results show in a time-varying typical urban (TU) channel that the proposed channel estimator provides better bit-error-rate (BER) performances than conventional algorithms such as the NLMS and RLS channel estimators.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.495-508
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• 2023

This paper proposes a method to find out the type and location information of Pauli X, Y, Z errors generated in quantum channels using only the quantum information processing part of the multiple-rate quantum turbo short-block code without external help from the classical information processing part. In order to obtain the location information of the Pauli X,Y error, n-auxiliary qubits and n-CNOT gates were inserted into the C[n,k,2] QSBC-QURC encoder. As a result, the maximum coding rate is limited to about 1/2 as the trade-off characteristics. The location information of the Pauli Z error for C[n,k,2] QSBC-QURC was obtained through the Clifford-based stabilizer measurement. The proposed method inherits all other characteristics of C[n,k,2] QSBC-QURC except for the coding rate.

• ETRI Journal
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• v.26 no.6
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• pp.615-621
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• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.549-552
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• 2003

In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3B
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• pp.202-211
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• 2002

Because wireless links are subject to disturbances and failures, it is important to support disconnected operations in mobile computing. Many schemes have been proposed to support the efficient disconnected operations. In this paper, we analyze and measure the computation time including disconnected operations to evaluate the performance of mobile computing on error prone wireless links. Mobile computation consists of three states: data hoarding, disconnected operation, and block states. We estimate the computation time using various parameters; error rate and recovery rate of wireless link, hoarding overhead, logging overhead, and reintegration overhead, etc. We can choose efficient strategies for disconnected operations and predict the performance using the results of this analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• Journal of the Korea Society for Simulation
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• v.15 no.4
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• pp.79-86
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• 2006

Data transmission in poor environment like underwater has considerably serious delay rate and ewer rate. Like this environment usually has heavy fluctuation of error rate and limited wireless communication state. Therefore, mechanism using in such environment has to be efficient and simple. This paper suggests a new block ack mechanism, called the Pervasive Block ACK (PBA), which transmits aggregated ACKs. This mechanism takes effect on reducing number of traffic, decreasing overhead and delay rate in poor environment networks like underwater. Additionally, we can expect energy consumption. We verify propriety and efficiency of PBA through describing numerical result based analytical formula in this paper.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.285-293
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• 1998

This paper presents unequal error protection and error concealment techniques far robust H.263 video transmission over mobile channels. The proposed error protection scheme has three major features. First, it has the capability of preventing the loss of synchronization information in H.263 video stream as much as possible that the H.263 decoder can resynchronize at the next decoding point, if errors are occurred. Secondly, it employs an unequal error protection scheme to support variable coding rates using rate compatible punctured convolutional (RCPC) codes, dividing the encoded stream into two classes. Finally, a macroblock-interleaving scheme is employed in order to minimize the corruption of consecutive macroblocks due to burst errors, which can make a proper condition for error concealment. In addition, to minimize the spatial error propagations due to the variable length codes, a fast resynchronization scheme at the group of block layer is developed for recovering subsequent error-free macroblocks following the damaged macroblock. futhermore, error concealment techniques based on both side match criterion and overlapped block motion compensation (OBMC) are employed at the source decoder so that it can not only recover the lost macroblock more accurately, but also reduce blocking artifacts. Experimental results show that the proposed scheme can be an effective error protection scheme since proper video quality can be maintained under various channel bit error rates.