• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.5
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• pp.211-221
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• 1998

Thermal behavior on the cylinder block of a 4-cylinder, 4-stroke 2.0L SOHC gasoline engine was numerically and experimentally analyzed. The numerical calculation was performed using the finite element method. The cylinder block was modelled as a three dimensional finite element by considering its geometry. The physical domain was devided into hexahedron elements. 16 thermocouples were installed at points of 2mm inside from cylinder wall near top ring of piston in cylinder block, which points have suffered major thermal loads and suggested as proper measurement points for engine design by industrial engineers. Under full load and 9$0^{\circ}C$ coolant temperature condition, temperature behavior of cylinder block according to engine speed were analyzed. The results showed that temperature rose gradually to conform to a function of 2nd~4th order of engine speed at intake side, exhaust and siamese side, respectively. As engine load was changed from 100 to 50% by 25% step, temperature curve also conformed to 2nd~7th order function of engine speed. Temperature differences by load condition were similar among 100, 75% and 50%. Under full load and coolant temperature of 11$0^{\circ}C$, temperature behavior were also analyzed and the result also showed conformance to 2n d~7th order function of engine speed. Temperature curve was transferred in parallel upwards corresponding coolant temperature rise.

• Korean Journal of Computational Design and Engineering
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• v.13 no.1
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• pp.36-44
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• 2008

This paper proposes a modeling and simulation process of a panel production line (PPL) in a shipyard. The panel production line is an assembly process to produce a main panel of a flat block and a curved block. In this paper, its activity analysis is carried out using expression of IDEF0, and its process is qualitatively and quantitatively analyzed and modeled by Petri Nets. A commercial discrete event simulation tool, $QUEST^{TM}$, is used for virtual PPL and simulation. The modeling results by Petri Net are mapped to elements of the simulation tool. Finally, an integrated simulation environment of PPL is implemented in order to efficiently utilize the virtual PPL model. With the help of IDEF0 and Petri Nets, we could systematically analyze and describe the PPL process that are characterized as being concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic. Also, the dynamic and concurrent activities of a PPL system were able to be simulated. A timing concept can be included into the Petri nets model to evaluate performance and dependability issues of the system.

• Journal of Navigation and Port Research
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• v.38 no.4
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• pp.421-427
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• 2014

In order to protect coastal facilities mainly from wave and current actions, the self-locking eco blocks constituting elements of protecting shore structures against scouring were designed. These blocks are adapted to the sloping bottom, coastal dunes, and submerged coastal pipelines, counteracting the destructive and erosive impulse action. A series of laboratory experiments has been conducted to investigate the reflection of water waves over and against a train of protruded or submerged shore structures and compare the reflecting capabilities of incident waves including wave forces. In this study the hydraulic model experiment was conducted to identify the performance of newly designed water affinity eco blocks to keep the coast slope and bottom mound from scouring by reduction of the wave reflection and to convince stability of the block placement. Revised design of each block element was also tested for field conditions. From the result of experiments, the field applicability of the developed blocks and placement was discussed afterward.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1124-1129
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• 2003

In mechanical design, design process is mainly composed of design, explanation and evaluation. In this paper, Using Genetic Algorithms (GA), Evolutionary computation is introduced as new design process. This method promote the efficiency and power of design. Due to the known characteristics of the stage, the approach basically involves a synthetic design method with the composition of building blocks representing the elements of mechanical objects. In order for the building blocks to be more suitable for representation and evolution of mechanical structures, Elementary Cell Blocks (ECBs) are introduced as new building blocks. In this paper, we have demonstrated the implementation of the approach with the design of gear systems.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.6
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• pp.144-155
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• 1999

An occupant analysis code SAFE (Safety Analysis For occupant crash Environment) is utilized to simulate and improve the crash performance of an energy absorbing steering system. The safety standard FMVSS 203 is simulated and used for design evaluations . Segments and contact elliposids are utilized to model the bod blocks and the components of the steering system with SAFE. Spring-damper elements and force-deflection characteristics are utilized to model the energy absorbing components such as the plate and the polyacetal molding. The plate absorbs the impact energy through tensile deformation . Whereas, the polyacetal molding absorbs the impact energy through compression. the body block test is carried out to validate tie simulation model, and real component tests are performed to extract the force-deflection curves . After the model is validated , the parameter study is carried out to evaluate the crash performance of the energy absorbing components. A performance measure is defined for the parameter study. Using the results of the parameter study and managing the orthogonal arrays, optimum design values of energy absorbing components are determined to minize the occupant injury.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.210-213
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• 2003

This paper presents a beamforming algorithm for the uplink application of a linear array antenna for WCDMA system. A steering beamforming algorithm is designed using a block DFT algorithm and its performance is analyzed and verified using computer simulations. Various environmental parameters such as the number of antenna elements, the number of users, the mobility of the target user, and the status of fast power control are reflected in the simulation study providing themselves as useful design and implementation guides for the reverse link beamforming of WCDMA system.

• Journal of the Korea Society of Computer and Information
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• v.19 no.9
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• pp.21-31
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• 2014

Singular value decomposition (SVD) has been widely used to identify unique features from a data set in various fields. However, a complex matrix calculation of SVD requires tremendous computation time. This paper improves the performance of a representative one-sided block Jacoby algorithm using a two-dimensional (2D) multi-core system. In addition, this paper explores an optimal multi-core system by varying the number of processing elements in the 2D multi-core system with the same 400MHz clock frequency and TSMC 28nm technology for each matrix-based one-sided block Jacoby algorithm ($128{\times}128$, $64{\times}64$, $32{\times}32$, $16{\times}16$). Moreover, this paper demonstrates the potential of the 2D multi-core system for the one-sided block Jacoby algorithm by comparing the performance of the multi-core system with a commercial high-performance graphics processing unit (GPU).

• Korean Journal of Human Ecology
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• v.17 no.3
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• pp.501-509
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• 2008

This research intends to help local small fashion industry to outgrow its limitation, preserving and developing environment-friendly dyeing tradition in Jeju renowned for persimmon juice dyeing. The study, then, aims to develop eco-friendly golf-wear designs, with maximizing advantages of natural dyeing (with persimmon juice, indigo plant, gallnut, cochineal, turmeric, and loess) such as rot-proofness, bacteria-proofness, stench-proofness and block of ultraviolet rays. The results are as follows: first, natural fabrics such as muslin(cotton 100%), linen(linen 100%) and spandex(mixed cotton 98%, polyurethane 2%) were developed into eco-friendly ones colored with various natural dye sources. Second, four kinds of golf-wear design were developed to stand out golf wear's natural image, focused on classic, neo-minimal style. The characteristic details and design elements of sportswear were added to basic golf wear design. Therefore, it is hopeful that those designs of naturally dyed golf wear for women could be utilized for other various purposes in the future.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.220-227
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• 2002

An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.