• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.103-109
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• 2008

This paper presents the architecture and design of intra prediction circuit for H.264 decoder. There are a total of 17 operational modes in the intra prediction of H.264- nine modes for a luma $4\times4$ block, four modes for a luma $16\times16$ block and four modes for a chroma $8\times8$ block. We extracted common operations included in all prediction modes and defined the common operations unit to perform those operations. The proposed circuit architecture sharing this unit in all prediction modes is systematic from the design point of view and efficient in terms of circuit size.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.43-49
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• 2014

In this paper, we consider the performance evaluation of space time block code (STBC)) with coordinate interleaved orthogonal design (CIOD) over time selective channel. In case of quasi static channel, STBC-CIOD satisfies full rate and full diversity (FRFD) property with the single symbol decoding. However in the time selective channel, the symbol interference degrades the system performance when we employ the single symbol decoding. We derive the union bound of the symbol error probability by evaluating the pairwise error probability in the first order Markov channel. We also present simulation results of STBC-CIOD with QPSK.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Journal of the Korean Geotechnical Society
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• v.21 no.10
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• pp.49-60
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• 2005

This paper presents the results of an investigation on the effects of design variables on the behavior of geosynthetic-reinforced modular block walls in a tiered arrangement using the finite-element method of numerical analysis. A parametric study was performed by varying the offset distance between the tiers and reinforcement length of the lower and upper tier using verified finite-element model. The finite-element analysis provided relevant information on the mechanical behavior of the tier wall and interaction mechanism between the upper and lower tier, which was otherwise difficult to obtain from the limit-equilibrium analysis based current design approaches. Practical implications of the findings obtained from this study in the current design approaches are discussed in great detail.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Journal of Practical Engineering Education
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• v.9 no.2
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• pp.107-117
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• 2017

here are many cases that take a software education as a required course for non-major students in university curriculums. However, non-major students are experiencing various difficulties in the process of learning programming languages, and there is also the opposite opinion in terms of their effectiveness. In this study, we developed a design based software education model (DBSEM) and curriculum to solve these problems and applied it to undergraduate non-undergraduate students for the last 8 years. In the proposed method, we provide a specialized educational tool such as 'block-based programming tool', but developed 'core module' and 'concept learning module' for computational thinking and applied 'prototype design module' and coding strategy based on it. As a result, non-major undergraduates could easily learn block-based scripting tools and acquire core concepts of computational thinking.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• Journal of the Korean Wood Science and Technology
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• v.17 no.2
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• pp.34-64
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• 1989

Corner block with anchor bolt(CBA) joint method used in knock-down type table furniture manufacturing can reduce the packing and transporting cost. Unfortunately. it also has the disastrous defect to be loosend and unstable during the service life mainly due to fatigue and creep(repeated and prolonged loading). So 22 joint groups constructed were tested to evaluate the effect of some design factors related to the size of side rail(apron). block attachment to side rail. and the number of anchor bolt as well as the effect of the type of corner block(mitered type vs. rectangular type) Usable strength from the stiffness coefficients of each joint group were analysed with SPSS /PC+ and described as the criteria of CBA joint construction. The conclusions were as follows: The height of side rail(50, 75 and 100 mm) and the addition of polyvinyl acetate(PVAc) emulsion in the corner block attactment to side rail had the effect on raising the usable strength of CBA joint with remarkable high significance. And the effect of 2 - anchor bolts was also superior to that of 1 - bolt significantly. However. the thickness of side rail(22 mm vs. 25 mm) had no effect on the strengthening the table joint rigidity. Mitered type corner block joint appeared to he recommendable for CBA jointed table construction rather than the rectangular type one regardless of the method of block attachment to side rail. The best result identified from Duncan's multiple comparison was in the construction with 25 mm thick and 100 mm height of side rail fastened using 2 - anchor bolts in mitered type corner block. But it would be reasonable to use 22 mm thick & 75 mm high side rail and mitered corner block with PVAc emulsion & 2 bolts considering the productivity and production cost down in the MDF furniture manufacturing industries.