• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.647-648
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• 2008

Traditional FTL and flash file systems based of NAND flash memory may not be adaptively applied to new fusion flash memory which combines the advantages of NAND and NOR flash memory. In this paper, we propose a FTL performance measurement tool using Multi Block Erase function of fusion flash memory. The performance measurement tool shows that multi block erase function can be effectively utilized in performance enhancement of garbage collection for fusion flash memory.

• Journal of International Society for Simulation Surgery
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• 제3권2호
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• pp.90-92
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• 2016

Horizontal bone defect in the anterior maxilla makes it difficult to place dental implant. The golden standard for bone augmentation is autogenous block bone graft. Tight contact with recipient site and rigid fixation are two key factors for successful block bone graft. Ramal bone graft has been the most reliable methods for dental implant field. However, the curvature of the alveolar ridge is different from ramal bone shape. Intraoperative trimming of ramal bone is cumbersome for surgeon. In this technical note, a simple way to design the ramal bone harvest using bone wax stent is reviewed.

• 전자공학회논문지A
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• 제29A권2호
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• pp.100-106
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• 1992

In this pape, we designed and implemented a hardware accelerator for the generation of bit map font from Hangul outline font description for LBP (Laser Beam Printer) and screen applications Whole system was implemented as a double size PC/AT application board which consists of processing bolck and display block. The processing block has a master processor (MC68000)and two slave processors which are MC56001 and KAFOG chip responsible for the short vector generation. In the display block, TMS34061 was used for monitor display and GP425 was used for LBP print out. The resolution of the monitor is 640$\times$480 and that of LBP is 2385$\times$3390. The current system called KHGB90-B generates about 100 characters per second where each character consists of 32$\times$32 bits

• 전자공학회논문지B
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• 제31B권9호
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

• 반도체디스플레이기술학회지
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• 제12권4호
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• pp.33-38
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• 2013

Image retrieval is one of the most exciting and fastest growing research fields in the area of multimedia technology. As the amount of digital contents continues to grow users are experiencing increasing difficulty in finding specific images in their image libraries. This paper proposes an efficient image descriptor which uses a local color and texture in the non-overlapped block images. To evaluate the performance of the proposed method, we assessed the retrieval efficiency in terms of ANMRR with common image dataset. The experimental trials revealed that the proposed algorithm exhibited a significant improvement in ANMRR, compared to Dominant Color Descriptor and Edge Histogram Descriptor.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1992년도 춘계학술대회 논문집
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• pp.297-300
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• 1992

For the most part of machine design, assembly drawing isaffected byits inserted parts. When a part is inserted in assembly, alreadyd stablished parting line is modified for reasonable representation. for example, break or trim fuction between the lines gives more recognizable drqwing. Most of parts is composed of such that point, line, arc, circle and block. If the part is composed of block, it is very difficult to operate because its attribution is unknown before exploding, but, It is very easy to operate except block. In this paper, it is required that basic feature recognition rules are caused by knowledge-based. This system which shows a good modify tool using AutoCAD system and ADS (Autocad Development System).

• 한국해양공학회지
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• 제18권3호
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• pp.26-31
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• 2004

This paper presents a process planning system that will generate and verify assembly sequences of block assemblies. It consists of a CAD interface system and an assembly sequence planning system. In developing this system, we used an open architecture CAD kernel for the CAD interface system, for visualizing the CAD model and the assembly sequences, and an expert system shell for the assembly sequence planning system. This paper also proposes a framework for the integration of all the steps required to automate the procedures, from design to production. The process planning system is demonstrated by a simple example.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• 한국안전학회지
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• 제15권1호
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• pp.19-27
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• 2000

This paper numerically deals with combined heat transfer in a enclosure with a block. The block affected by hot wall is located centrally in the enclosure with a radiating gray gas. The discrete ordinate method(DOM) was used for solving the radiative transfer equation. Both laminar and turbulent cases were investigated for various Rayleigh number and standard k-$\varepsilon$ model was adopted to turbulent case. The effects of optical thickness, wall emissivity and fluid-solid thermal conductivity ratio are investigated on the flow and temperature fields. This study shows that as the wall emissivity decreases, the temperature distribution gradually becomes uniform and the heat transfer is reduced in enclosure. It is expected that this study can help to design the energy system related to the combined heat transfer and operate it safely.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2006년도 춘계학술대회
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.