• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.12
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• pp.2213-2220
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• 2017

This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Korean Journal of Soil Science and Fertilizer
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• v.44 no.2
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• pp.176-180
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• 2011

Rice production depended on the weed control. The purpose of this study was conducted to evaluate the influence of tillage with chemical amendments + 5 cm flooded, no-tillage without Chinese milk vetch + 5 cm flooded (NTNT 5 cm), no-tillage amended with Chinese milk vetch + 5 cm flooded (NTCM 5 cm), and no-tillage amended with Chinese milk vetch + 10 cm flooded (NTCM 10 cm) on weed occurrence and yield of rice in paddy. Triplicate experimental plots were laid out in a randomized complete block design and compared by employing least significant difference. The dry weights of weeds in NTCM 5 cm and NTCM 10 cm were 11% and 4% level of NTNT 5 cm (p<0.05) and were 3.2 times and 1.2 times more than in conventional tillage system. In addition, the Aneilema keisak and Ludwigia prostrata were significantly increased in NTNT 5 cm (p<0.05). The yield of rice grain in NTCM 10 cm was 2.6 times more than in NTNT 5 cm and was 89% level of conventional tillage system. Our findings suggest that NTCM 10 cm should be enhance of weed control as well as improving of yield of rice in paddy.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The korean journal of orthodontics
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• v.39 no.2
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• pp.105-111
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• 2009

Objective: To estimate the effects of bracket material type on enamel decalcification during orthodontic treatment, this study analyzed the adhesion level of mutans streptococci (MS) to orthodontic bracket materials in vivo. Methods: Three different types of orthodontic bracket materials were used: stainless steel, monocrystalline sapphire, and polycrystalline alumina. A balanced complete block design was used to exclude the effect of positional variation of bracket materials in the oral cavity. Three types of plastic individual trays were made and one subject placed the tray in the mouth for 12 hours. Then, the attached bacteria were isolated and incubated on a mitis salivarius media containing bacitracin for 48 hours. Finally, the number of colony forming units of MS was counted. The experiments were independently performed 5 times with each of the 3 trays, resulting in a total of 15 times. Mixed model ANOVA was used to compare the adhesion amount of MS. Results: There was no difference in colony forming units among the bracket materials irrespective of jaw and tooth position. Conclusions: This study suggested that the result of quantitative analysis of MS adhesion to various orthodontic bracket materials in vivo may differ from that of the condition in vitro.

• Journal of the Korean Association of Oral and Maxillofacial Surgeons
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• v.30 no.4
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• pp.331-338
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• 2004

Stress transfer to the surrounding tissues is one of the factors involved in the design of dental implants. Unfortunately, insufficient data are available for stress transfer within the regenerated bone surrounding dental implants. The purpose of this study was to investigate the concentration of stresses within the regenerated bone surrounding the implant using three-dimensional finite element stress analysis method. Stress magnitude and contours within the regenerated bone were calculated. The $3.75{\times}10-mm$ implant (3i, USA) was used for this study and was assumed to be 100% osseointegrated, and was placed in mandibular bone and restored with a cast gold crown. Using ANSYS software revision 6.0, a program was written to generate a model simulating a cylindrical block section of the mandible 20 mm in height and 10 mm in diameter. The present study used a fine grid model incorporating elements between 165,148 and 253,604 and nodal points between 31,616 and 48,877. This study was simulated loads of 200N at the central fossa (A), at the outside point of the central fossa with resin filling into screw hole (B), and at the buccal cusp (C), in a vertical and $30^{\circ}$ lateral loading, respectively. The results were as follows; 1. In case the regenerated bone (bone quality type IV) was surrounded by bone quality type I and II, stresses were increased from loading point A to C in vertical loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, concentrated on the top of the cylindrical collar loading point B and C in vertical loading. And, In case the regenerated bone (bone quality type IV) was surrounded by bone quality type III, stresses were increase from loading point A to C in vertical loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, B and C in vertical loading. 2. In case the regenerated bone (bone quality type IV) was surrounded by bone quality type I and II, stresses were decreased from loading point A to C in lateral loading. Stresses according to the depth of regenerated bone were concentrated on the top of the cylindrical collar in loading point A and B, distributed along the implant evenly in loading point C in lateral loading. And, In case the regenerated bone (bone quality type IV) was surrounded by bone quality type III, stresses were decreased from loading point A to C in lateral loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, B and C in lateral loading. In summary, these data indicate that both bone quality surrounding the regenerated bone adjacent to implant fixture and load direction applied on the prosthesis could influence concentration of stress within the regenerated bone surrounding the cylindrical type implant fixture.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.221-231
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• 2013

Exchanging personal health information(PHI) is an essential process of healthcare services using information and communication technology. But the process have the inherent risk of information disclosure, so the PHI should be protected to ensure the reliability of healthcare services. In this paper, we designed encryption module for wearable personal health devices(PHD). A main goal is to guarantee that the real-time encoded and transmitted PHI cannot be allowed to be read, revised and utilized without user's permission. To achieve this, encryption algorithms as DES and 3DES were implemented in modules operating in Telos Rev B(16bit RISC, 8Mhz). And the experiments were performed in order to evaluate the performance of encryption and decryption using vital-sign measured by PHD. As experimental results, an block encryption was measured the followings: DES required 1.802 ms and 3DES required 6.683 ms. Also, we verified the interoperability among heterogeneous devices by testing that the encrypted data in Telos could be decoded in other machines without errors. In conclusion, the encryption module is the method that a PHD user is given the powerful right to decide for authority of accessing his PHI, so it is expected to contribute the trusted healthcare service distribution.

• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.486-491
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• 2008

This paper describes a model identification method that has been applied to a commercial 12-inch RTP (rapid thermal processing) equipment with an ultimate aim to develop a high-performance advanced controller. Seven thermocouples are attached on the wafer surface and twelve tungsten-halogen lamp groups are used to heat up the wafer. To obtain a MIMO balanced state space model, multiple SIMO (single-input multiple-output) identification with highorder ARX models have been conducted and the resulting models have been combined, transformed and reduced to a MIMO balanced state space model through a balanced truncation technique. The identification experiments were designed to minimize the wafer warpage and an output linearization block has been proposed for compensation of the nonlinearity from the radiation-dominant heat transfer. As a result from the identification at around 600, 700, and $800^{\circ}C$, respectively, it was found that $y=T(K)^2$ and the state dimension of 80-100 are most desirable. With this choice the root-mean-square value of the one-step-ahead temperature prediction error was found to be in the range of 0.125-0.135 K.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.64-72
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• 2012

Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.