• Title/Summary/Keyword: block design

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Impacts of Flooding Depths on Weed Occurrence and Yield in No-tillage Paddy Field Covered with Chinese Milk Vetch (무경운 자운영 피복 논에서 담수 깊이가 잡초발생과 수량에 미치는 영향)

  • Hong, Kwang-Pyo;Lee, Young-Han
    • Korean Journal of Soil Science and Fertilizer
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    • v.44 no.2
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    • pp.176-180
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    • 2011
  • Rice production depended on the weed control. The purpose of this study was conducted to evaluate the influence of tillage with chemical amendments + 5 cm flooded, no-tillage without Chinese milk vetch + 5 cm flooded (NTNT 5 cm), no-tillage amended with Chinese milk vetch + 5 cm flooded (NTCM 5 cm), and no-tillage amended with Chinese milk vetch + 10 cm flooded (NTCM 10 cm) on weed occurrence and yield of rice in paddy. Triplicate experimental plots were laid out in a randomized complete block design and compared by employing least significant difference. The dry weights of weeds in NTCM 5 cm and NTCM 10 cm were 11% and 4% level of NTNT 5 cm (p<0.05) and were 3.2 times and 1.2 times more than in conventional tillage system. In addition, the Aneilema keisak and Ludwigia prostrata were significantly increased in NTNT 5 cm (p<0.05). The yield of rice grain in NTCM 10 cm was 2.6 times more than in NTNT 5 cm and was 89% level of conventional tillage system. Our findings suggest that NTCM 10 cm should be enhance of weed control as well as improving of yield of rice in paddy.

An Emulation System for Efficient Verification of ASIC Design (ASIC 설계의 효과적인 검증을 위한 에뮬레이션 시스템)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.17-28
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    • 1999
  • In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

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Quantitative analysis of mutans streptococci adhesion to various orthodontic bracket materials in vivo (다양한 교정용 브라켓 원재료에 부착하는 mutans streptococci 양의 비교분석)

  • Yu, Jin-Kyoung;Ahn, Sug-Joon;Lee, Shin-Jae;Chang, Young-Il
    • The korean journal of orthodontics
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    • v.39 no.2
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    • pp.105-111
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    • 2009
  • Objective: To estimate the effects of bracket material type on enamel decalcification during orthodontic treatment, this study analyzed the adhesion level of mutans streptococci (MS) to orthodontic bracket materials in vivo. Methods: Three different types of orthodontic bracket materials were used: stainless steel, monocrystalline sapphire, and polycrystalline alumina. A balanced complete block design was used to exclude the effect of positional variation of bracket materials in the oral cavity. Three types of plastic individual trays were made and one subject placed the tray in the mouth for 12 hours. Then, the attached bacteria were isolated and incubated on a mitis salivarius media containing bacitracin for 48 hours. Finally, the number of colony forming units of MS was counted. The experiments were independently performed 5 times with each of the 3 trays, resulting in a total of 15 times. Mixed model ANOVA was used to compare the adhesion amount of MS. Results: There was no difference in colony forming units among the bracket materials irrespective of jaw and tooth position. Conclusions: This study suggested that the result of quantitative analysis of MS adhesion to various orthodontic bracket materials in vivo may differ from that of the condition in vitro.

FINITE ELEMENT ANALYSIS OF CYLINDER TYPE IMPLANT PLACED INTO REGENERATED BONE WITH TYPE IV BONE QUALITY (IV형의 골질로 재생된 골내에 식립된 원통형 임플란트의 유한요소법적 연구)

  • Kim, Byung-Ock;Hong, Kug-Sun;Kim, Su-Gwan
    • Journal of the Korean Association of Oral and Maxillofacial Surgeons
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    • v.30 no.4
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    • pp.331-338
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    • 2004
  • Stress transfer to the surrounding tissues is one of the factors involved in the design of dental implants. Unfortunately, insufficient data are available for stress transfer within the regenerated bone surrounding dental implants. The purpose of this study was to investigate the concentration of stresses within the regenerated bone surrounding the implant using three-dimensional finite element stress analysis method. Stress magnitude and contours within the regenerated bone were calculated. The $3.75{\times}10-mm$ implant (3i, USA) was used for this study and was assumed to be 100% osseointegrated, and was placed in mandibular bone and restored with a cast gold crown. Using ANSYS software revision 6.0, a program was written to generate a model simulating a cylindrical block section of the mandible 20 mm in height and 10 mm in diameter. The present study used a fine grid model incorporating elements between 165,148 and 253,604 and nodal points between 31,616 and 48,877. This study was simulated loads of 200N at the central fossa (A), at the outside point of the central fossa with resin filling into screw hole (B), and at the buccal cusp (C), in a vertical and $30^{\circ}$ lateral loading, respectively. The results were as follows; 1. In case the regenerated bone (bone quality type IV) was surrounded by bone quality type I and II, stresses were increased from loading point A to C in vertical loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, concentrated on the top of the cylindrical collar loading point B and C in vertical loading. And, In case the regenerated bone (bone quality type IV) was surrounded by bone quality type III, stresses were increase from loading point A to C in vertical loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, B and C in vertical loading. 2. In case the regenerated bone (bone quality type IV) was surrounded by bone quality type I and II, stresses were decreased from loading point A to C in lateral loading. Stresses according to the depth of regenerated bone were concentrated on the top of the cylindrical collar in loading point A and B, distributed along the implant evenly in loading point C in lateral loading. And, In case the regenerated bone (bone quality type IV) was surrounded by bone quality type III, stresses were decreased from loading point A to C in lateral loading. And stresses according to the depth of regenerated bone were distributed along the implant evenly in loading point A, B and C in lateral loading. In summary, these data indicate that both bone quality surrounding the regenerated bone adjacent to implant fixture and load direction applied on the prosthesis could influence concentration of stress within the regenerated bone surrounding the cylindrical type implant fixture.

Design of Real-time Vital-Sign Encryption Module for Wearable Personal Healthcare Device (착용형 개인 건강관리 장치를 위한 실시간 생체신호 암호화 모듈의 설계)

  • Kim, Jungchae;Yoo, Sun Kook
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.221-231
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    • 2013
  • Exchanging personal health information(PHI) is an essential process of healthcare services using information and communication technology. But the process have the inherent risk of information disclosure, so the PHI should be protected to ensure the reliability of healthcare services. In this paper, we designed encryption module for wearable personal health devices(PHD). A main goal is to guarantee that the real-time encoded and transmitted PHI cannot be allowed to be read, revised and utilized without user's permission. To achieve this, encryption algorithms as DES and 3DES were implemented in modules operating in Telos Rev B(16bit RISC, 8Mhz). And the experiments were performed in order to evaluate the performance of encryption and decryption using vital-sign measured by PHD. As experimental results, an block encryption was measured the followings: DES required 1.802 ms and 3DES required 6.683 ms. Also, we verified the interoperability among heterogeneous devices by testing that the encrypted data in Telos could be decoded in other machines without errors. In conclusion, the encryption module is the method that a PHD user is given the powerful right to decide for authority of accessing his PHI, so it is expected to contribute the trusted healthcare service distribution.

Model Identification for Control System Design of a Commercial 12-inch Rapid Thermal Processor (상업용 12인치 급속가열장치의 제어계 설계를 위한 모델인식)

  • Yun, Woohyun;Ji, Sang Hyun;Na, Byung-Cheol;Won, Wangyun;Lee, Kwang Soon
    • Korean Chemical Engineering Research
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    • v.46 no.3
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    • pp.486-491
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    • 2008
  • This paper describes a model identification method that has been applied to a commercial 12-inch RTP (rapid thermal processing) equipment with an ultimate aim to develop a high-performance advanced controller. Seven thermocouples are attached on the wafer surface and twelve tungsten-halogen lamp groups are used to heat up the wafer. To obtain a MIMO balanced state space model, multiple SIMO (single-input multiple-output) identification with highorder ARX models have been conducted and the resulting models have been combined, transformed and reduced to a MIMO balanced state space model through a balanced truncation technique. The identification experiments were designed to minimize the wafer warpage and an output linearization block has been proposed for compensation of the nonlinearity from the radiation-dominant heat transfer. As a result from the identification at around 600, 700, and $800^{\circ}C$, respectively, it was found that $y=T(K)^2$ and the state dimension of 80-100 are most desirable. With this choice the root-mean-square value of the one-step-ahead temperature prediction error was found to be in the range of 0.125-0.135 K.

Design of a computationally efficient frame synchronization scheme for wireless LAN systems (무선랜 시스템을 위한 계산이 간단한 초기 동기부 설계)

  • Cho, Jun-Beom;Lee, Jong-Hyup;Han, Jin_Woo;You, Yeon-Sang;Oh, Hyok-Jun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.64-72
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    • 2012
  • Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.

Low Power Implementation of Integrated Cryptographic Engine for Smart Cards (스마트카드 적용을 위한 저전력 통합 암호화 엔진의 설계)

  • Kim, Yong-Hee;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.80-88
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    • 2008
  • In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

Effects of Different Levels of Vitamin-Mineral Premixes on Growth Performance, Nutrient Digestibility, Carcass Characteristics and Meat Quality of Growing-Finishing Pigs

  • Tian, J.Z.;Lee, J.H.;Kim, J.D.;Han, Y.K.;Park, K.M.;Han, In K.
    • Asian-Australasian Journal of Animal Sciences
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    • v.14 no.4
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    • pp.515-524
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    • 2001
  • Two experiments using growing and finishing pigs (Landrace$\times$Duroc$\times$Yorkshire) were conducted to determine the effects of different levels of vitamins and trace minerals (VTM) on growth performance, nutrient digestibility, carcass characteristics and meat quality of growing-finishing pigs, and to evaluate the suitability of vitamin-mineral levels commonly used in the swine industry in Korea. A total of 120 three crossbred (Landrace$\times$Duroc$\times$Yorkshire) growing (Experiment I: 20.90 0.44 kg average initial body weight) and finishing (Experiment II: 53.55 0.97 kg average initial body weight) were used in 6 and 9 weeks feeding trials, respectively. Pigs were allotted on the basis of sex and weight to 5 treatments with 6 replications per treatment with 4 pigs per pen in a completely randomized block design. Treatments were: 1) control, 2) fat soluble vitamin 200% vs. control, 3) water soluble vitamin 200% vs. control, 4) trace mineral 50% vs. control, 5) trace mineral 200% vs. control. In experiment I, during the overall experimental period (0 to 6 weeks, 21 to 54 kg body weight), ADG of the 200% trace mineral supplemented group was significantly higher than that of the 50% trace mineral supplemented group. There were no significant differences among other the treatments. Digestibility of crude protein was lowest in mineral 50% supplemented group (p<0.05). Calcium digestibility was significantly higher in the 200% fat soluble vitamin supplemented group than in the other treatments (p<0.05). In experiment II, during the overall experimental period (0 to 9 weeks, 54 to 106 kg body weight), growth performance was not significantly affected by dietary vitamin and trace mineral levels. However, increasing level of water soluble vitamins at the level of 200% compared to control had a tendency to improve the overall growth performance. Overall carcass characteristics except for carcass length did not differ among pigs fed the dietary treatments. Loin eye area, pH, drip loss and shear force of meat were not affected by dietary vitamin and trace mineral levels. There was a trend for less fat content (%) in pork when the level of vitamin and trace mineral was increased, but the difference was not significant. Flavor score was the lowest in control and highest in the 200% fat soluble vitamin supplemented group (p<0.05). Juiciness of muscle was lower in the 200% fat soluble vitamin supplemented group than other dietary treatments, except for trace mineral 50% supplemented group (p<0.05). Based on these results, it is suggested that "typical" commercial levels of vitamin and trace minerals used by feed companies in Korea are sufficient to meet requirement for the maximum growth of growing-finishing pigs. Our results suggests that a reduction in trace mineral levels in commercial diets could be considered to reduce feed cost and nutrient excretion with economic and environmental benefits.

Design of a Low Phase Noise Vt-DRO Based on Improvement of Dielectric Resonator Coupling Structure (유전체 공진기 결합 구조 개선을 통한 저위상 잡음 전압 제어 유전체 공진기 발진기 설계)

  • Son, Beom-Ik;Jeong, Hae-Chang;Lee, Seok-Jeong;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.6
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    • pp.691-699
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    • 2012
  • In this paper, we present a Vt-DRO with a low phase noise, which is achieved by improving the coupling structure between the dielectric resonator and microstrip line. The Vt-DRO is a closed-loop type and is composed of 3 blocks; dielectric resonator, phase shifter, and amplifier. We propose a mathematical estimation method of phase noise, using the group delay of the resonator. By modifying the coupling structure between the dielectric resonator and microstrip line, we achieved a group delay of 53 nsec. For convenience of measurement, wafer probes were inserted at each stage to measure the S-parameters of each block. The measured S-parameter of the Vt-DRO satisfies the open-loop oscillation condition. The Vt-DRO was implemented by connecting the input and output of the designed open-loop to form a closed-loop. As a result, the phase noise of the Vt-DRO was measured as -132.7 dBc/Hz(@ 100 kHz offset frequency), which approximates the predicted result at the center frequency of 5.3 GHz. The tuning-range of the Vt-DRO is about 5 MHz for tuning voltage of 0~10 V and the power is 4.5 dBm. PFTN-FOM is -31 dBm.