• Title/Summary/Keyword: block LDPC code

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The Effect of Block Interleaving in an LDPC-Turbo Concatenated Code

  • Lee, Sang-Hoon;Joo, Eon-Kyeong
    • ETRI Journal
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    • v.28 no.5
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    • pp.672-675
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    • 2006
  • The effect of block interleaving in a low density parity check (LDPC)-turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed-Solomon (RS) code. Thus, an LDPC-turbo concatenated code can show better performance than the conventional RS-turbo concatenated code. Furthermore, the performance of an LDPC-turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.

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Construction of Block-LDPC Codes based on Quadratic Permutation Polynomials

  • Guan, Wu;Liang, Liping
    • Journal of Communications and Networks
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    • v.17 no.2
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    • pp.157-161
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    • 2015
  • A new block low-density parity-check (Block-LDPC) code based on quadratic permutation polynomials (QPPs) is proposed. The parity-check matrix of the Block-LDPC code is composed of a group of permutation submatrices that correspond to QPPs. The scheme provides a large range of implementable LDPC codes. Indeed, the most popular quasi-cyclic LDPC (QC-LDPC) codes are just a subset of this scheme. Simulation results indicate that the proposed scheme can offer similar error performance and implementation complexity as the popular QC-LDPC codes.

Performance and Iteration Number Statistics of Flexible Low Density Parity Check Codes (가변 LDPC 부호의 성능과 반복횟수 통계)

  • Seo, Young-Dong;Kong, Min-Han;Song, Moon-Kyou
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.1
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    • pp.189-195
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    • 2008
  • The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

A Weighted Block-by-Block Decoding Algorithm for CPM-QC-LDPC Code Using Neural Network

  • Xu, Zuohong;Zhu, Jiang;Zhang, Zixuan;Cheng, Qian
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.8
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    • pp.3749-3768
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    • 2018
  • As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

Protograph-Based Block LDPC Code Design for Marine Satellite Communications (해양 위성 통신을 위한 프로토그래프 기반 블록 저밀도 패리티 검사 부호 설계)

  • Jeon, Ki Jun;Ko, Byung Hoon;Myung, Se-Chang;Lee, Seong Ro;Kim, Kwang Soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.7
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    • pp.515-520
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    • 2014
  • In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

High-rate LDPC Coded OFDM System for Image Transmission over Rayleigh Fading Channel (레일리 페이딩 채널에서 이미지 전송을 위한 고속 LDPC부호를 적용한 OFDM 시스템)

  • Choi, Sang-Min;Moon, Byung-Hyun
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.233-235
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    • 2005
  • As a class of block codes, LDPC code with any desired code rate and code length is easily constructed. In OFDM system high data transmission is possible, In this paper, we examined the performance of four high-rate(0.75, 0.8, 0.889, 09412) LDPC coded OFDM in image transmission over Rayleigh fading channel. The high-rate of 0.9412 LDPC coded OFDM system obtained about 12dB gain over the OFDM at BER of $10^{-3}$ over Rayleigh fading channel. Also, the PSNR of code rate 0.9412 LDPC coded OFDM system at SNR=10dB is given by 18.8047dB where uncoded OFDM system gives 9.7303 dB.

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Construction of Multiple-Rate Quasi-Cyclic LDPC Codes via the Hyperplane Decomposing

  • Jiang, Xueqin;Yan, Yier;Lee, Moon-Ho
    • Journal of Communications and Networks
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    • v.13 no.3
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    • pp.205-210
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    • 2011
  • This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

Detection of Colluded Multimedia Fingerprint using LDPC and BIBD (LDPC와 BIBD를 이용한 공모된 멀티미디어 핑거프린트의 검출)

  • Rhee Kang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.43 no.5 s.311
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    • pp.68-75
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    • 2006
  • Multimedia fingerprinting protects multimedia content from illegal redistribution by uniquely marking every copy of the content distributed to each user. Differ from a symmetric/asymmetric scheme, fingerprinting schemes, only regular user can know the inserted fingerprint data and the scheme guarantee an anonymous before recontributed data. In this paper, we present a scheme which is the algorithm using LDPC(Low Density Parity Check) for detection of colluded multimedia fingerprint and correcting errors. This proposed scheme is consists of the LDPC block, Hopfield Network and the algorithm of anti-collusion code generation. Anti-collusion code based on BIBD(Balanced Incomplete Block Design) was made 100% collusion code detection rate about the linear collusion attack(average, AND and OR) and LD% block for the error bits correction confirmed that can correct error until AWGN 0dB.

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

  • Shin, Kyung-Wook;Kim, Hae-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.24-33
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    • 2012
  • This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

Tanner Graph Based Low Complexity Cycle Search Algorithm for Design of Block LDPC Codes (블록 저밀도 패리티 검사 부호 설계를 위한 테너 그래프 기반의 저복잡도 순환 주기 탐색 알고리즘)

  • Myung, Se Chang;Jeon, Ki Jun;Ko, Byung Hoon;Lee, Seong Ro;Kim, Kwang Soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.8
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    • pp.637-642
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    • 2014
  • In this paper, we propose a efficient shift index searching algorithm for design of the block LDPC codes. It is combined with the message-passing based cycle search algorithm and ACE algorithm. We can determine the shift indices by ordering of priority factors which are effect on the LDPC code performance. Using this algorithm, we can construct the LDPC codes with low complexity compare to trellis-based search algorithm and save the memory for storing the parity check matrix.