• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.25-34
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• 2005

In this paper, we analyzed and measured the electrical crosstalk characteristics of a triplex transceiver module for ethernet Passive optical networks(EPONS). And we improved the electrical crosstalk levels using Dummy ground lines with signal lines. The triplex transceiver module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and a analog photodetector as a community antenna television signal receiver. And there are integrated on silicon substrate. The digital receiver and analog receiver sensitivity have to meet -24 dBm at $BER=10^{-l2}$ and -7.7 dBm at 44 dB SNR. And the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the Dummy ground line with $100\;{\mu}m$ space from signal lines and separates 4 mm among devices respectively, is satisfied the electrical crosstalk level compared to simple structure. This proposed structure can be easily implemented with design convenience and greatly reduced the silicon substrate size about $50\%$.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2
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• pp.50-61
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• 1995

A time scale modification method yielding rate-modified speech while conserving the characteristic of speech was implemented in real-time using a goneral purpose digital signal processor. Time scale modification changed pronunciation speed only, producing a time difference between the input signal and the modified signal, making it impossible to implement it in real-time. In this thesis, a system was implemented to remove the time difference between the input and modified signals. Speech signals slowed down or speeded up by a physical time scale modification method, such as adjusting the motor speed of the cassett tape recorder, was used as the input signal. Physical modification that controled only the inter speed of the cassette tape player distorted the pitch period of the original speech. In this study, a real-time system was implemented so that the pitch-distorted speech was reconstructed back to the original by fractional sampling pitch shifting using an FIR filter, and this signal was time scale modified to match the cassette tape recorder motor speed using SOLA time-scale medification. In experiments using speech signals medifiedby the proposed method, results obtained using a 16-bit resolution ADSP2101 processor and using computer simulations employing floating point operations showed about the same average frame signal-to-noise ratio of about 20 dB.

• Journal of the Korean Chemical Society
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• v.26 no.5
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• pp.333-339
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• 1982

Substituent effects of substrate and leaving group for the reaction of substituted ${\beta}$-phenylethyl arenesulfonates with pyridine were determined conductometrically in acetonitrile at 50∼70$^{\circ}$C. The substituent effect in substrate is not so significant than expected, but still the electron donating substituent shows the slight acceleration to give a small negative ${\rho}$ value and Hammett plots show slight curvature on the acting substituents, even though it is not so remarkable than that of benzyl system. These results represent a little bit the favorable bond breaking at the transition state by the electron donating substituents. The effects of leaving group in the arenesulfonates in which the rate constants are decreased by electron donating substituents, while electron withdrawing groups presented the reverse effects. Hammett ${\rho}$ value is significantly smaller than that of p-nitrobenzyl arenesulfonates and thus, the mechanism should be closer to tight $S_N2$ one. Especially 2,5-dichlorobenzenesulfonate was more accelerated than expected at the additivity of substituents. This facts showed that dichlorobenzenesulfonate anion is more stabilized by the great electron withdrawing substituents at transition state.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.1-10
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• 2012

Improving operating frequency of processors is no longer today's issues; a multiprocessor technique which integrates many processors has received increasing attention. Currently, high-performance processors that integrate 64 or 128 cores are developing for large data processing over 2, 4, or 8 processor cores. This paper proposes an optimal many-core processor for synthesizing guitar sounds. Unlike the previous research in which a processing element (PE) was assigned to support one of guitar strings, this paper evaluates the impacts of mapping different numbers of PEs to one guitar string in terms of performance and both area and energy efficiencies using architectural and workload simulations. Experimental results show that the maximum area energy efficiencies were achieved at PEs=24 and 96, respectively, for synthesizing guitar sounds with sampling rate of 44.1kHz and 16-bit quantization. The synthesized sounds were very similar to original guitar sounds in their spectra. In addition, the proposed many-core processor was 1,235 and 22 times better than TI TMS320C6416 in area and energy efficiencies, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.82-94
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• 2015

In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.105-113
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• 2013

RAID systems have been widely used by connecting several disks in parallel structure. to resolve the delay and bottleneck of data I/O. Recently, SSD based RAID systems are emerging since SSDs have better I/O performance than HDD. However, endurance and power consumption problems due to frequent write operation in SSD based RAID system should be resolved. In this paper, we propose a de-duplication method of parity disk in SSD based RAID system with expensive update cost. The proposed method segments chunk of parity data into small pieces and removes duplicate data, therefore, it can reduce wear-leveling and power consumption by decreasing write operation for duplicated parity data. Experimental results show that bit update rate of the proposed method is 16% in total disk, 31% in parity disk less than that of existing method in RAID-6 system using EVENODD erasure code, and the power consumption of the proposed method is 30% less than that of existing method. Besides the proposed method is 12% in total disk, 32% in parity disk less than that of existing method in RAID-5 system, and the power consumption of the proposed method is 36% less than that of existing method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1518-1531
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• 1999

The reconstructed images from highly compressed MPEG or H.263 data have noticeable image degradations, such as blocking artifacts near the block boundaries, corner outliers at cross points of blocks, and ringing noise near image edges, because the MPEG or H.263 quantizes the transformed coefficients of 8$\times$8 pixel blocks. A post-processing algorithm has been proposed by authors to reduce quantization effects, such as blocking artifacts, corner outliers, and ringing noise, in MPEG-decompressed images. Our signal-adaptive post-processing algorithm reduces the quantization effects adaptively by using both spatial frequency and temporal information extracted from the compressed data. The blocking artifacts are reduced by one-dimensional (1-D) horizontal and vertical low pass filtering (LPF), and the ringing noise is reduced by two-dimensional (2-D) signal-adaptive filtering (SAF). A comparison study of the subjective quality evaluation using modified single stimulus method (MSSM), the objective quality evaluation (PSNR) and the computation complexity analysis between the signal-adaptive post-processing algorithm and the MPEG-4 VM (Verification Model) post-processing algorithm is performed by computer simulation with several MPEG-4 image sequences. According to the comparison study, the subjective image qualities of both algorithms are similar, whereas the PSNR and the comparison complexity analysis of the signal-adaptive post-processing algorithm shows better performance than the VM post-processing algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.539-549
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• 1999

In this paper, the bit error rare (BER) performance of DS/CDMA DQPSK communication system in the presence of multi access interference, impulsive noise and Nakagami fading is investigated. The DS/CDMA DQPSK communication system adopts Maximum Ratio Combining (MRC) diversity reception and error correcting BCH code technique to enhance system performance. Using the derived error probability equation, the error rate performance of DS/CDMA DQPSK communication system has been evaluated and shown in figures to discuss as a function of impulsive index(A), Gaussian noise to impulsive noise power ratio($\Gamma$'), multi access interference(Κ), Nakagami fading parameter(m), the number of diversity branch (Ｌ), the number of error correction symbol (t), PN code sequence length(N) and $E_b/N_0$. The error performance of DS/CDMA-MDPSK signals improve by adopting MRC diversity and BCH(15,7) coding technique in the environment of impulsive noise plus Nagakami fading. From the results, we known that proposed system is affected by multi access interference, impulsive noise and Nakagami fading in radio communication system environment. Also, BER performance of DS/CDMA DQPSK communication system cam be improved increasing either the power of desired signal or the value of Gaussian noise to impulsive noise power ratio. And BCH(15,7) code technique is more effective to restrain the affection of multi access, interference, impulsive noise and Nakagami fading in DS/CDMA DQPSK communication system than MRC diversity reception technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.506-519
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• 1999

An adaptive array antennal and a CCI canceller have been considered as techniques for cancelling Multi-User Interference(MUI) in Direct Sequence Code Division Multiple Access(DS-CDMA) system. These techniques have different problems respectively in the process of cancelling MUI as the number of users increases. For that reason, the scheme which can cancel MUI effectively by compensating for the problems of each of the techniques has been required. For the scheme, the technique to connect an adaptive array antenna and a CoChannel Interference(CCI) canceller in cascade form has been studied. In the existing study about the cascade connection method, the effect of cancelling MUI about two interference signals is analyzed, but the analysis for the quantitative BER(Bit Error Rate) improvement according to the number of users is not considered. Therefore, in this paper, we have analyzed the degree of BER performance improvement quantitatively according to the number of users by introducing the receiving system, which connects an adaptive array antenna and a CCI canceller to a DS-CDMA system in cascade form. For the method of analyzing the performance, we have performed the theoretical analysis and the simulation, considering the case of adopting only an adaptive array antenna and of cascade connection respectively, and having compared and analyzed the results. From the results, it is confirmed that in the case of adopting only an adaptive array antenna, the problems occur in the process of cancelling MUI according to the number of users and the receiving direction of interference signals, and can be compensated by the cascade connection method. In conclusion, we have known that MUI is cancelled effectively by using the cascade connection method, and the much better BER performance improvement is obtained.