• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.259-267
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• 1999

In this paper, a C-band 6-bit phase shifter is designed and fabricated and design techniques for each phase bit are represented. We applied the loaded line type to $5.625^{\circ},\;11.25^{\circ},\;22.5^{\circ}\;and\;45^{\circ}$ phase bits and the hybrid coupled type to $90^{\circ}$ phase bit and the switched line type to $180^{\circ}$ phase bit, respectively on a microstrip copper substrate.

• Journal of Information Display
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• v.2 no.2
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• pp.1-6
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• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.2
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• pp.111-120
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• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.5
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• pp.197-202
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• 2002

In this paper, the characteristics of the household AC power line network is analyzed for the low bit rate powerline communication (PLC) in the frequency range from 10㎑ to 450㎑ The PLC channel transfer characteristics including its characteristic impedance are derived based on the network topology which is constructed with the household power lines loaded with the various types of electric apparatus. Both the distributed circuit analysis and the lumped circuit model based analysis are applied for the characterization of the PLC channel and the results are compared by the computer simulations. The analysis illustrates very well the adverse effects caused by the loading of electric apparatus and as well those casued by the reflection of wavers in the household AC Power line communication network.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2559-2561
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• 2002

This paper presents a systematic method of probing channel characteristics and communication reliabilities of home PLC (power line communication) network applied to the Internet accessed control of home appliances. The effects of the three performance deterioating factors, i.e., additive noise, channel attenuation, and intersymbol interference, can be systematically measured by applying the channel probing waveform in the frequency range from 100kHz to 450kHz. The agreement between the derived probability of bit error and the measured probability of bit error supports the validity of the proposed approach of probing home power line channel characteristics. The experimental results performed with the constructed test-bed applying the proposed channel probing method also support the feasibility of commercially deploying the PLC modem installed home appliances and their services for the Internet accessed home automation.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.305-307
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• 2001

In this paper, the household AC power line network is characterized for the low bit rate power line communication (PLC) in the frequency range from 10kHz to 450kHz. Various types of electric apparatus and the power lines constitute the network topology, and the PLC channel transfer function and the channel impedance are derived based on the constructed network topology. The channel characteristics derived with the lumped circuit model and the distributed circuit model are compared using the computer simulations. The effect of the wave reflection and signal distortions are also investigated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.279-282
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• 2002

In this paper, we discuss influence of process condition on contact resistance in WSix deposition process. In the WSix deposition process, we confirmed that word line to bit line contact resistance(WBCR) due to temperature of word line WSix deposition among various process condition split experiment. RTP treatment, d-poly ion implantation dose and thickness was estimated a little bit influence on contact resistance. Also, life time of shower head in the process chamber for WSix deposition related to contact resistance. The results obtained in this study are applicable to process control and electrical characteristics for high reliability and high density DRAM's.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.11
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• pp.960-965
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• 2015

In this paper, a coupled line directional coupler using an LUC(Low-pass filter Unit Cell) of artificial transmission line is presented. The conventional coupled line coupler is limited in length by the ${\lambda}/4$ transmission line while the proposed coupling structure is implemented smaller than $90^{\circ}$ by inserting the phase delay line between two coupled line, reduced in physical size by configuring a phase delay line with an LUC having the characteristics of a typical transmission line in a particular frequency. A coupler having -10 dB coupling factor at the center frequency of 700 MHz is designed, fabricated. The measured result agrees well with that of conventional one. The length of the fabricated coupled line coupler has about 45 % in length compared to the conventional one.