• Journal of Platform Technology
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• v.6 no.4
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.11
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• pp.1959-1975
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• 2011

Adaptive Bit Loading (ABL) in Multiple-Input Multiple-Output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) is often used to achieve the desired Bit Error Rate (BER) performance in wireless systems. In this paper, we discuss some of the bit loading algorithms, compare them in terms of the BER performance, and present an effective and concise Adaptive Grouped Loading (AGL) algorithm. Furthermore, we propose a "weight factor" for loading algorithm to converge rapidly to the final solution for various data rate with variable Signal to Noise Ratio (SNR) gaps. In particular, we consider the bit loading in near optimal Singular Value Decomposition (SVD) based MIMO-OFDM system. While using SVD based system, the system requires perfect Channel State Information (CSI) of channel transfer function at the transmitter. This scenario of SVD based system is taken as an ideal case for the comparison of loading algorithms and to show the actual enhancement achievable by our AGL algorithm. Irrespective of the CSI requirement imposed by the mode of the system itself, ABL demands high level of feedback. Grouped Loading (GL) would reduce the feedback requirement depending upon the group size. However, this also leads to considerable degradation in BER performance. In our AGL algorithm, groups are formed with a number of consecutive sub-channels belonging to the same transmit antenna, with individual gains satisfying predefined criteria. Simulation results show that the proposed "weight factor" leads a loading algorithm to rapid convergence for various data rates with variable SNR gap values and AGL requires much lesser CSI compared to GL for the same BER performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2304-2310
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• 2009

This paper presents WSK(wavelet shift keying) that can be improved to bit transmission rate in the digital communication. An algorithm of the conventional modulation is carried out that the scaling function and wavelet are encoded to 1(mark) and 0(space) for the input binary data, respectively. A new modulation technique that uses four carrier frequencies is proposed. Four carrier frequencies are defined as scaling function, inversed scaling function, wavelet, and inversed wavelet, which are encoded to 10, 11, 00 and 01 respectively. An algorithm of the proposed demodulation is decode to the original data using four correlation. As a results of simulation, we confirmed that the proposed method was improved to the performance at twice for the bit transmission rate.

• Convergence Security Journal
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• v.12 no.4
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• pp.85-90
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• 2012

DES is a 64-bit binary, and each block is divided into units of time are encrypted through an encryption algorithm. The same key as the symmetric algorithm for encryption and decryption algorithms are used. Conversely, when decryption keys, and some differences may apply. The key length of 64 bits are represented by two ten thousand an d two 56-bit is actually being used as the key remaining 8 bits are used as parity check bits. The 64-bit block and 56-bit encryption key that is based on a total of 16 times 16 modifier and spread through the chaos is completed. DES algorithm was chosen on the strength of the password is questionable because the most widely available commercially, but has been used. In addition to the basic DES algorithm adopted in the future in the field by a considerable period are expected to continue to take advantage of the DES algorithm effectively measures are expected to be in the field note.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• Journal of The Korean Association of Information Education
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• v.25 no.6
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• pp.995-1003
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• 2021

As the need for artificial intelligence (AI) education, which will become the core of the upcoming intelligent information society rises, the national level is also focusing attention by including artificial intelligence-related content in the curriculum. In this study, the PASPA education program was presented to enhance students' creative problem-solving ability in the process of solving problems in daily life through supervised machine learning. And Micro:bit, a physical computing tool, was used to enhance the learning effect. The teaching and learning process applied to the PASPA education program consists of five steps: Problem Recoginition, Argument, Setting data standard, Programming, Application and evaluation. As a result of applying this educational program to students, it was confirmed that the creative problem-solving ability improved, and it was confirmed that there was a significant difference in knowledge and thinking in specific areas and critical and logical thinking in detailed areas.

• Journal of the Korean Institute of Landscape Architecture
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• v.30 no.1
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• pp.1-10
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• 2002

The purpose of this article is to examine land use change in the fringe area of a metropolitan city through multi-temporal data analysis. Change detection has been regarded as one of the most important applications for utilization of remotely sensed imageries. Conventionally, two images were used for change detection, and Arithmetic calculators were generally used on the process. Meanwhile, multi-temporal change detection for a large number of images has been carried out. In this paper, a digital land-use map and three Landsat TM data were utilized for the multi-temporal change detection Each urban area map was extracted as a base map on the process of multi-temporal change detection. Each urban area map was converted to bit image by using boolean logic. Various urban change types could be obtained by stacking the urban area maps derived from the multi-temporal data using Geographic Information System(GIS). Urban change type map was created by using the process of piling up the bit images. Then the urban change type map was compared with each land cover map for the change detection. Dalseo-gu of Daegu city and Hwawon-eup of Dalsung-gun, the fringe area of Daegu Metropolitan city, were selected for the test area of this multi-temporal change detection method. The districts are adjacent to each other. Dalseo-gu has been developed for 30 yeais and so a large area of paddy land has been changed into a built-up area. Hwawon-eup, near by Dalseo-gu, has been influenced by the urbanization of Dalseo-gu. From 1972 to 1999, 3,507.9ha of agricultural area has been changed into other land uses, while 72.7ha of forest area has been altered. This agricultural area was designated as a 'Semi-agricultural area'by the National landuse Management Law. And it was easy for the preserved area to be changed into a built-up area once it would be included as urban area. Finally, the method of treatment and management of the preserved area needs to be changed to prevent the destruction of paddy land by urban sprawl on the urban fringe.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.992-1001
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• 1996

Radix sort scans the data twice in a pass, to search bit 0s of the items being sorted and store them into the lowest address, and to search bit 1s and st ore them into the following addresses. This doubles the sorting time. In this paper, we introduce Reverse Radix Sort Algorithm, in which the data being sorted are sacnned just once and write upward from the lowest address if it is 0 and downward from the highest address if it is 1. The algorithm is simple and the hardware sorter implemented by this method shows very high sorting sped. Hardware implementation requires two separate pocket memories, register, an upward increasing address counter, a downward decreasing address counter, and comparator. The software simulation of Reverse Radix Sor Algorithm performs sorting in the speed of 54.9ms per 10 thousand of 8 bit digit data, but the hardware sorter spends 5.3ms to sort the same number of data.