• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.651-652
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• 2012

Wireless monitoring and hybrid mobile web have become an emerging area of research in recent year. This paper deals with the design and implementation of mobile web page for sensing data monitoring. The mobile web monitoring system for sensing data transmission is implemented by 8-bit AVR microcontroller and bluetooth communication module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1862-1867
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• 1999

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• Journal of the Korean Chemical Society
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• v.31 no.1
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• pp.71-78
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• 1987

A simple and inexpensive digital data acquisition system for general use in chemical laboratory was constructed. Since the system has its own 12-bit 4K memory, it can be used by itself to capture the fast signals. The system can also be used with Apple Ⅱ+ microcomputer for acquisition and processing of data.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.163-172
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• 1995

In this paper, the bit-level 1-dimensionl systolic array for modular multiplication are designed. First of all, the parallel algorithms and data dependence graphs from Walter's Iwamura's methods based on Montgomery Algorithm for modular multiplication are derived and compared. Since Walter's method has the smaller computational index points in data dependence graph than Iwamura's, it is selected as the base algorithm. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays ale obtained and then are evaluated by various criteria. Modifying the array derived from 〔0,1〕 projection direction by adding a control logic and serializing the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for modular expandable and is good for fault tolerance due to unidirectional paths. And so, it is suitable for RSA Cryptosystem which deals with the large size and many consecutive message blocks.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.195-205
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• 2014

The ultra-high definition television (UHDTV) has been considered as a next generation broadcsating service. However the conventional digital terrestrial transmission system cannot afford the required transmission data rate of UHDTV, and thus adopting ultra-high order constellation, such as 4096-QAM, into the conventional DTT systems has been studied. In particular, when the ultra-high order constellation is adopted into the digital video broadcasting-2nd generation terrestrial (DVB-T2) unequal-error protection (UEP) properties of a codeword of an error correction coding and ultra-high order constellations should be properly matched by bit mapper in order to enhance the decoding performance. Because long codeword results in a heavy computational complexity to design the bit mapper, the DVB-T2 divided it into cascaded blocks, the bit interleaver and the bit-to-cell DEMUX, and there have been many researches related to each block. However, there are few published study related to design methodology of bit interleaver. In this respect, this paper proposes a design methodology of the bit interleaver and presents bit interleavers of 1024-QAM and 4096-QAM according to the proposed design algorithm. The newly designed interleavers improved the decoding performance of the error correction coding by maximally 0.6 dB SNR over both of AWGN and random fading channel.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.15 no.2
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• pp.121-125
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• 2015

In this paper, we propose a method that extracts features from character patterns using the fractal dimension of chaos theory. The input character pattern image is converted into time-series data. Then, using the modified Henon system suggested in this paper, it determines the last features of the character pattern image after calculating the box-counting dimension, natural measure, information bit, and information (fractal) dimension. Finally, character pattern recognition is performed by statistically finding each information bit that shows the minimum difference compared with a normalized character pattern database.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.196-200
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• 1987

In this paper A NET-CUE System is designed and implemented for tramsmission of the network cuing informations with using data packet broad casting techniques. This system is composed with encoder and decoder. To show the performance of this system An eye height and bit error rate are cheched. The eye height is greater than 74% and The bit error rate is less than 4.6 * 10 The exper imental results show that this system provides a good quality of the operation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.384-388
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• 1986

This paper describes the design and fabrication of an integrated circuit that can detect the teletext signal included in a composite video signal. The circuit that is based on the comparatorlevel sampling method can detect a stable data signal even from an external circuit with large variation. It has been fabricated by the SST bipolar standard process. Its chip size is $2.5x3.78mm^2$.