• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.129-133
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers and fuzzy rules. Therefore, By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.6
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• pp.77-81
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• 2008

In the deeply coupled GPS/INS integrated systems, if the integration filter update period is longer than the period of GPS navigation data, the loss of correlation values occurs due to the bit transition. This problem can be resolved when data wipe off(DWO) is used. However, general DWO methods requires heavy computation or cannot be applied continuously. This paper proposes an effective DWO method using carrier phase discriminator In order to show validity of the proposed method, simulations were carried out. The simulation results show that the data bit is accurately estimated and conform that the loss of correlation values and the error of code phase is small.

• International Journal of Railway
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• v.3 no.2
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• pp.39-45
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• 2010

The RF-CBTC (Radio Frequency-Communication Based Train Control) System is a communication system in railroad systems. The communication method of RF-CBTC system is the wireless between the wayside device and on-board device. The wayside device collects its location and speed from each train and transmits the distance from the forwarding train to the speed-limit position to it. The on-board device controlling device controls the speed optimum for the train. In the case of the RF-CBTC system used in Korea, transmission frequency is 2.4 [GHz]. It is the range of ISM(Industrial Scientific and Medical equipment) band and transmission of voice and data is performed by CDMA (Code Division Multiple Access) method. So noises are made in the AWGN (Additive White Gaussian Noise) and fading environment. Currently, the SNR (Signal to Noise Ratio) is about 20 [dB], so due to bit errors made by noises, transmission of reliable information to the train is not easy. Also, in the case that two tracks are put to a single direction, it is needed that two trains transmit reliable voice and data to a wayside device. But, by noises, it is not easy that just a train transmits reliable information. In this paper, we estimated the BER (Bit Error Rate) related to the SNR of voice and data transmission in the environment such as AWGN and fading from the RF-CBTC system using the CDMA method. Also, we supposed the SNR which is required to meet the BER standard for voice and data transmission. By increasing the processing gain that is a ratio of chip transmission to voice and data transmission, we made possible voice and data transmission from maximally two trains to a wayside device, and demonstrated it by using Matlab program.

• The KIPS Transactions:PartB
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• v.11B no.6
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• pp.625-632
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• 2004

Since the H.264 encoding adopts both forward prediction and hi-direction prediction modes and exploits Variable Length Coding(VLC), the amount of data generated from video encoder varies as Flaying time goes by. The fixed bit rate encoding system which has limited transmission channel capacity uses a buffer to control output bitstream It's necessary to control the bitstream to maintain within manageable range so as to protect buffer from overflow or underflow. With existing bit amount control algorithms, the $\lambda_{MODE}$ which is relationship between distortion value and quantization parameter often excesses normal value to end up with video error. This paper proposes an algorithm to protect buffer from overflow or underflow by introducing a new quantization parameter against distortion value of H.264 video data. The test results of 6 exemplary data show that the proposed algorithm has the same PSNR as and up to 8% reduced bit rate against existing algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.35-42
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• 2005

This paper proposes a new reseeding methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR). In the proposed reseeding scheme, a test cube with large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR and Multiple Polynomial can be represented by adding just 1 bit to encoding data. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.160-172
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• 2014

Although Wyner-Ziv (WZ) video coding proves useful for applications employing encoders having restricted computing resources, the WZ decoder has a problem of excessive decoding complexity. It is mainly due to its iterative LDPC channel decoding process which repeatedly requests incremental parity data after iterative channel decoding of parity data received at each request. In order to solve the complexity problem, we divide bit planes into two groups and estimate the minimum required number of parity requests separately for the two groups of bit planes using bit plane correlation. The WZ decoder executes the iterative decoding process only after receiving parity data corresponding to the estimated minimum number of parity requests. The proposed method saves about 71% of the computing time in the LDPC decoding process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.