• Proceedings of the Korea Society for Industrial Systems Conference
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• 2007.02a
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• pp.35-39
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• 2007

We applied digital image processing about BitMap file structure in this research and studied about digital communication system. digital record saving devices can express 'High' and 'Low' as all data. Only, digital technique that two expression methods is used into several expenditures. People and communication that are far away by development of digital technology, became smooth. We wished to make communication system taking advantage of digi-tech. This system was made for communication with disabled and normal person specially. To communication method that we are studied such BitMap file handling image communication system. The goal of this contribution is to present the overview of basic algorithms for image processing using BitMap.

• Proceedings of the Korea Database Society Conference
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• 1995.12a
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• pp.173-176
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• 1995

본 논문에서 다루는 내용은 멀티미디어 정보처리시 이용되는 여러 신호 처리용 하드웨어에서 필요로 하는 벡터 트랜스퍼메이션(Vector Transformation)및 오소그날 트랜스퍼메이션(Orthogonal Transformation)에 유용할 뿐만 아니라 여러 형태의 다양한 연산(elementary function including trigonometric functions)을 하나의 단일화된 알고리즘으로 구현할 수 있게 한 CORDIC(Coordinate Rotation Digit Computer)연산［1］［2］에 관한 연구이다. CORDIC 연산기를 실현함에 있어서 고속 연산을 위해 고속 가산기(fast adder)로서 CSA(Carry Save Adder)를 선택하는데, 본 논문의 연구 초점은 CORDIC연산기를 하드웨어로 실현하기 전에 Bit-Level의 시뮬레이터를 통하여, CSA의 특징상 발생할 수 있는 문제점어 대해 설명하고, 해결 방법［3］을 이용하여 원하는 값에 접근하는가를 확인하여 다양한 Bit의 조작으로 오차의 정도에 따라 유효한 CORDIC연산기를 실현하는데 도움이 되고자 한다.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.652-654
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• 2015

최근 ICT융합 기술의 비약적인 발전에 따라 소형 휴대가 가능한 다양한 종류의 생체신호 측정센서의 출현으로 유헬스케어 관련 기술이 비약적으로 발전하게 되면서, 실시간으로 발생하는 생체데이터에 대한 효율적인 처리가 중요하게 되었다. 따라서 본 논문에서는 M2M기반에서 발생되는 생체데이터의 효율적인 전송을 위해 LZW(Lempel-Ziv-Welch) 압축 알고리즘과, BitVector압축 알고리즘을 결합한 LZW-BitVector 압축 알고리즘을 제안한다.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.2
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• pp.1-9
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• 2012

This study proposed a method to determine the number and location of bus information terminals (BIT), which is a device to provide passengers with bus arrival time at bus stops in a Bus Information System (BIS). In low-density area, it is not efficient to survey bus demands such as the number of passengers at all bus stops due to time and cost. This kind of a survey would, however, competently cover all bus stops if performed inside the bus. The number of riding-on and -off passengers is observed for every bus stop, and this data collection is repeated over all day. Data obtained from the survey are aggregated each bus stop. This study defines Utility Index (UI), an aggregate each bus stop. Bus stops are ranked according to UI and determined for a BIT within budget limitation. As a case study, a bus line in Jeju island, Korea, was dealt with. This case showed that the more aggregate the better data quality. This study is expected to contribute to solving a location problem of BITs in a BIS.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of Sensor Science and Technology
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• v.27 no.4
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• pp.254-258
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• 2018

A Wi-Fi signal network (WSN) system is introduced in this paper. This system consists of several data-transmitting sensor modules and a data-receiving server. Each sensor module and the server contain a unique intranet IP address. A piezoelectric accelerometer with a bandwidth of 12 kHz, a 24-bit analog-digital converter with a sampling rate of 15.625 kS/s, a 32-bit microprocessor unit, and a 1-Mbps Wi-Fi module are used in the data-transmitting sensor module. A 300-Mbps router and a PC are used in the server. The system is verified using an accelerometer calibrator. The voltage output from the sensor is converted into 24-bit digital data and transmitted via the Wi-Fi module. These data are received by a Wi-Fi router connected to a PC. The input frequencies of the accelerometer calibrator (320 Hz, 640 Hz, and 1280 Hz) are used in the data transfer verification. The received data are compared to the data retrieved directly from the analog-to-digital converter used in the sensor module. The comparison shows that the developed system represents the original data considerably well. Theoretically, the system can acquire vibration signals from 600 sensor modules at an accelerometer bandwidth of 15.625 kHz. However, delay exists owing to software processes, multiplexing between sensor modules, and the use of non-real time operating system. Hence, it is recommended that this system may be used to acquire vibration signals with up to 10 kHz, which is approximately 70% of the theoretical maximum speed of the system. The system can be upgraded using parts with higher performance

• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.881-886
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• 2007

This study was to develope a vibrotactile display system using windows media player from digital audio signal. WMPlayer10SDK system which was plug-in tool by microsoft windows media player provided its video and audio signal information. The audio signal was tried to be change into vibrotactile display. Audio signal had 4 sections such as 8bit, 16bit, 24bit, and 32bit. Each section was computed its frequency and vibrato scale. And data was transferred to 38400bps network port(COM1) for vibration. Using this system was able to develop the music suit which presented tactile feeling of music beyond sound. Therefore, it may provide cross modal technology for fusion technology of human senses.

• Journal of the Korea Society of Computer and Information
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• v.17 no.10
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• pp.11-23
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• 2012

To achieve efficient code size reduction, this paper proposes a new compressed instruction set architecture for the OpenRISC architecture. The new instructions and their corresponding formats are designed by the profiling information of the existing instruction usage. New 16-bit instructions and 32-bit instructions are proposed to compressed the existing 32-bit instructions and instruction sequences, respectively. The proposed instructions can be classified into three types. The first is the new 16-bit instructions for the frequent normal 32-bit instructions such as add, load, store, branch, and jump instructions. The second type is the new 32-bit instructions for the consecutive two load instructions, two store instructions, and 32-bit data mov instructions. Finally, two new 32-bit instructions are proposed to compress function prolog and epilog code, respectively. OpenRISC hardware decoder is extended to support the new instructions. Experiments show that the efficiency of code size reduction improves by an average of 30.4% when compared to the OR1200 instruction set architecture without loss of execution performance.