• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.229-232
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• 2000

AAL2 has been adopted for bandwidth-efficient trans-mission of low bit tate traffic over ATM networks in ITUT and ATM Forum. Since ATM/AAL2 is expected to be used as a switching technology in third-generation mobile access networks and mobile data traffic is expected to increase rapidly in near future, there must be a need for efficient scheduling scheme satisfying the QoS requirement of ow bit rate voice as well as the one of high bit rate data. In this paper, we propose a new class-scheduling scheme to improve data packet loss probability, while Qos of voice traffic is guaranteed, when data traffic is multiplexed together with mobile voice traffic into a single ATM VCC. The proposed scheme can efficiently support data traffic by assigning a time threshold value to voice traffic. Through simulation study, we show that the proposed scheme does not only achieve better efficiency for providing both mobile voice and data services than HOL class-scheduling scheme and normal FIFO scheme, but also guarantees mean voice packet delay under a certain criteria.

• 전자공학회논문지B
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• 제31B권4호
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• 한국통신학회논문지
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• 제31권5A호
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• pp.517-525
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• 2006

본 논문은 다수의 RFID 태그가 사용되고 있는 환경에서 고속 필터링을 수행하기 위한 필터링 엔진을 설계한다. 이를 위하여 우리는 고속 라우터나 방화벽에 적용되었던 고속 패킷 필터링 기법이 RFID 데이터 필터링과 매우 유사함을 보이고 그 중 대표적인 기법인 Bit Parallelism 기반의 Aggregated Bit Vector(ABV)를 고속 RFID 필터링 엔진에 적용한다. 또한, RFID 데이터 필터링의 성향을 관찰한 결과 태그 인식 및 필터 부합의 시간적 중복성을 발견하고 두 가지 캐쉬(태그 캐쉬, 필터 캐쉬)를 적용하여 추가적인 필터링 성능 향상을 꾀하였다. 설계한 RFID 고속 필터링 엔진의 성능 평가를 위해 프로토타입 애플리케이션을 제작하여 시뮬레이션을 수행하였다. 결과로써 기존의 순차적인 RFID 데이터 필터링에 비해 고속의 필터링 성능을 보이며 특히 필터의 수가 증가할수록 필터링의 효율이 높아짐을 보인다.

• 전자공학회논문지C
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• 제34C권11호
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• 대한전자공학회논문지TC
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• 제42권8호
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• pp.11-16
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• 2005

본 논문은 스크램블링(Scrambling), 길쌈부호화(Convolutional Encoding), 펑처링(Puncturing), 인터리빙(Interleaving) 등과 같은 연산에 공통적으로 필요한 비트 조작(Bit Manipulation)을 효율적으로 지원하기 위한 비트 조작 연산 가속기를 제안한다. 기존의 DSP는 곱셈 및 가산 연산을 기본으로 연산기가 구성되어 있으며 워드 단위로 동작을 함으로 비트 조작 연산의 경우 비효율적인 연산을 수행할 수밖에 없다. 그러나 제안한 가속기는 비트 조작 연산을 다수의 데이터에 대해 병렬 쉬프트와 XOR 연산, 비트 추출 및 삽입 연산을 효율적으로 수행할 수 있다. 제안한 가속기는 VHDL로 구현 하여 삼성 $0.18\mu m$ 표준 셀 라이브러리를 이용하여 합성하였으며 가속기의 게이트 수는 1,700개에 불과하다. 제안한 가속기를 통해 스크램블링, 길쌈부호화, 인터리빙을 수행시 기존의 DSP에 비해 $40\~80\%$의 연산 사이클의 절감이 가능하였다.

• 한국컴퓨터정보학회논문지
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• 제29권7호
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• pp.11-20
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• 2024

본 논문에서는 생성 모델을 이용한 데이터 프리 양자화에서 발생할 수 있는 지식 격차를 줄이기 위하여 BAG (Bit-width Aware Generator)와 채널 어텐션 기반 중간 레이어 지식 증류를 제안한다. 생성 모델을 이용한 데이터 프리 양자화의 생성자는 오직 원본 네트워크의 피드백에만 의존하여 학습하기 때문에, 양자화된 네트워크의 낮은 bit-width로 인한 감소된 수용 능력 차이를 학습에 반영하지 못한다. 제안한 BAG는 양자화된 네트워크와 동일한 bit-width로 양자화하여, 양자화된 네트워크에 맞는 합성 이미지를 생성하여 이러한 문제를 완화한다. 또한, 양자화된 네트워크와 원본 모델 간의 지식 격차를 줄이는 것 역시 양자화에서 매우 중요한 문제이다. 이를 완화하기 위해 제안한 채널 어텐션 기반 중간 레이어 지식 증류는 학생 모델이 교사 모델로부터 어떤 채널에 더 집중해서 학습해야 하는지를 가르친다. 제안한 기법의 효율성을 보이기 위해, CIFAR-100에서 학습한 원본 네트워크를 가중치와 활성값을 각각 3-bit로 양자화하여 학습을 수행하였다. 그 결과 56.14%의 Top-1 Accuracy를 달성하였으며, 베이스라인 모델인 AdaDFQ 대비 3.4% 정확도를 향상했다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제18권6호
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• pp.1619-1637
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• 2024

In today's highly digitized landscape, securing digital communication is paramount due to threats like hacking, unauthorized data access, and network policy violations. The response to these challenges has been the development of cryptography applications, though many existing techniques face issues of complexity, efficiency, and limitations. Notably, sophisticated intruders can easily discern encrypted data during transmission, casting doubt on overall security. In contrast to encryption, steganography offers the unique advantage of concealing data without easy detection, although it, too, grapples with challenges. The primary hurdles in image steganography revolve around the quality and payload capacity of the cover image, which are persistently compromised. This article introduces a pioneering approach that integrates image steganography and encryption, presenting the BitPatternStego method. This novel technique addresses prevalent issues in image steganography, such as stego-image quality and payload, by concealing secret data within image pixels with identical bit patterns as their characters. Consequently, concerns regarding the quality and payload capacity of steganographic images become obsolete. Moreover, the BitPatternStego method boasts the capability to generate millions of keys for the same secret message, offering a robust and versatile solution to the evolving landscape of digital security challenges.

• 대한한방내과학회지
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• 제25권4호
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• pp.274-288
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• 2004

Objectives : This study was designed to evaluate the effect on cytotoxicity of Bojungikki-tang(BIT) in human lung cancer H460 cells. Methods : BIT-induced cell death was confirmed as apoptosis characterized by chromatin condensation and increase of the $sub-G_1$, DNA content. It was tested whether the water extract of BIT affects the cell cycle regulators such as, p2l/Cipl, p27/Kipl, cyclin $B_1$. Results : The data showed that treatment of BIT decreased the viability of H460 cells in a dose-dependent manner. p2l/Cip1 is gradually decreased by the addition of the cells with BIT extract. Interestingly, p27/Kip1 is not detected for 24 hr after the addition of BIT extract, however, after 24 hr, p27/Kipl markedly increased. In addition, cyclin $B_1$, decreased in a time dependent manner after the addition of the water extract. The activation of caspase -3 protease was further confirmed by degradation of procaspase-8 protease andpoly(ADP-ribose) polymerase(P ARP) by BIT in H460 cells. Moreover, BIT induced the increase of Bak expression. Conclusion : These results suggest that the extract of BIT exerts anticancer effects to induce the death of human lung cancer H460 cells via down regulation of cell cycle regulators such as p2l/Cip1, and cyclin B1 or up regulation of cell cycle regulators such as p27/Kip1. Moerover results suggest that BIT induces an apoptosis in H460 cells via activation of intrinsic caspase cascades.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.794-796
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• 2000

This paper analyzes the method of cascading 74LS163 4-Bit Binary Counters. The 74LS163 4-Bit Binary Counter has synchronous LD. CLR functions and especially ENT, ENP, RCO to cascade some chips in order to count more 4bit binary number. The maximum operating frequency may vary according to the method of cascading. The Data sheet from Texas Instruments introduces two methods, The Ripple Carry Mode Circuit and The Carry Look Ahead Circuit, and shows that The Carry Look Ahead Circuit is more efficient than the other. However, there are only little information for user to understand and apply this to other circuits. Thus, we not only analyzed the two methods but also compared with each other in the point of performance.