• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.172-175
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• 2004

This paper analyzes the effects of Ge profiles shape of SiGe heterojunction bipolar transistors (HBT's) for high frequency application. Device simulations using ATLAS/BLAZE for the SiGe HBT with trapezoidal or triangular Ge profile are carried out to optimize the device performance. An HBT with $15\%$ triangular Ge profile shows higher cut-off frequency and DC current gain than that with $19\%$ trapezoidal Ge profile. The cut-off frequency and DC gain are increased from 42GHz to 84GHz and from 200 to 600, respectively. The SiGe HBT has been fabricated using a production CVD reactor.

• Nuclear Engineering and Technology
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• v.54 no.2
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• pp.501-506
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• 2022

Long turn-off time limits high frequency operation of Bipolar Junction Transistors (BJTs). Turn-off time decreases with increases in the recombination rate of minority carriers at switching transients. Fast neutron irradiation on a Si BJT incurs lattice damages owing to the displacement of silicon atoms. The lattice damages increase the recombination rate of injected holes with electrons, and decrease the hole lifetime in the base region of pnp Si BJT. Fast neutrons generated from a beryllium target with 30 MeV protons by an MC-50 cyclotron were irradiated onto pnp Si BJTs in experiment. The experimental results show that the turn-off time, including the storage time and fall time, decreases with increases in fast neutron fluence. Additionally, it is confirmed that the base current increases, and the collector current and base-to-collector current amplification ratio decrease due to fast neutron irradiation.

• Nuclear Engineering and Technology
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• v.55 no.11
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• pp.4238-4245
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• 2023

In order to predict the lifetime of InP Heterojunction Bipolar Transistor (HBT) devices and related circuits in the space radiation environment, a novel model including gamma radiation effects is proposed in this paper. Based on the analysis of radiation-induced device degradation effects including both DC and AC characteristics, a set of empirical expressions describing the device degradation trend are presented and incorporated into the Keysight model. To validate the effective of the proposed model, a series of radiation experiments are performed. The correctness of the novel model is validated by comparing experimental and simulated results before and after radiation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.1-7
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• 2007

Class AB bipolar linear transconductors for high frequency applications ire proposed. They consist of a voltage follower, a resistor, and a current follower. The follower circuits are realized by translinear cells or unity-gain buffers. The proposed transconductors are simulated using an 8 GHz bipolar transistor-arrary parameter. Simulation results show that the transconductor using translinear cells has better linearity than one using unity-gain buffers whereas the latter has better temperature stability and higher input resistance than the former. In order to test their high frequency applicability, the transconductors are used to implement an 4th order IF bandpass filter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.7-12
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• 2004

An improved extraction method considering ac current crowding effect is investigated to determine intrinsic ( $C_{\mu}$) and extrinsic ( $C_{\mu}$) base-collector capacitances of bipolar junction transistors separately. The drawbacks of conventional methods are pointed out, and the improved extraction equations are derived from a cutoff mode equivalent circuit with the ac crowding capacitance. The frequency response curves of modeled current and power gains using the extracted values of $C_{\mu}$ and $C_{\mu}$ have much better agreements with measured ones than those of the conventional methods, verifying the accuracy of the improved technique.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.103-111
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• 2017

In this study, the thermomechanical stress and fatigue analysis of a high voltage and high current (3,300 V/1200 A) insulated gate bipolar transistor (IGBT) module used for electric locomotive applications were performed under thermal cycling condition. Especially, the reliability of the copper wire and the ribbon wire were compared with that of the conventional aluminum wire. The copper wire showed three times higher stress than the aluminum wire. The ribbon type wire showed a higher stress than the circular type wire, and the copper ribbon wire showed the highest stress. The fatigue analysis results of the chip solder connecting the chip and the direct bond copper (DBC) indicated that the crack of the solder mainly occurred at the outer edge of the solder. In case of the circular wire, cracking of the solder occurred at 35,000 thermal cycles, and the crack area in the copper wire was larger than that of the aluminum wire. On the other hand, when the ribbon wire was used, the crack area was smaller than that of the circular wire. In case of the solder existing between DBC and base plate, the crack growth rate was similar regardless of the material and shape of the wire. However, cracking occurred earlier than chip solder, and more than half of the solder was failed at 40,000 cycles. Therefore, it is expected that the reliability of the solder between DBC and base plate would be worse than the chip solder.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.303-304
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• 2009

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine. ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.