• KEPCO Journal on Electric Power and Energy
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• 제6권2호
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• pp.119-122
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• 2020

With recent ESS (Energy Storage System) fire accident, the fault protection performance is becoming more important. However, there has never been any experiments with the protection performance on the faults in the ESS system level. In this study, the effect of AC ground fault and IGBT (Insulated Gate Bipolar mode Transistor) short-circuit failure on MW class ESS was performed experimentally for the first time in the world. First of all, the effect of the AC single line ground fault on battery was analyzed. Moreover, the transient voltage was investigated as a function of the battery capacity and the power level. Finally, the breaking capability and insulation performance of ESS were examined under PCS short-circuit fault condition. Through the tests, it was found that ESS protection system safely blocked the faulty current regardless of the faults, whereas the electronic parts such as IGBT and MC (Magnetic Contactor) were broken by the fault current. Also, the electrical breakdown in ESS resulted from the transient voltage during the protection process.

• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.135-140
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• 2016

In this study, we developed the solution-processed PMMA-$HfO_x$ hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-$HfO_x$ hybrid ReRAM were compared to those of PMMA- and $HfO_x$-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-$HfO_x$ hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and $HfO_x$-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the $HfO_x$ into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-$HfO_x$ hybrid ReRAM and $HfO_x$-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in $HfO_x$ film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-$HfO_x$ films showed an excellent flexibility without defect generation.

• ETRI Journal
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• 제39권5호
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• 센서학회지
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• 제24권5호
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• 한국표면공학회지
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• 제46권5호
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• pp.192-196
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• 2013

Stainless steels (AISI 316L) are carburized by Inductively coupled plasma using $CH_4$ and Ar gas. The ${\gamma}_c$ phase(S-phase) is formed on the surface of stainless steel after carburizing process. The XRD peak of carburized samples is shifted to lower diffracting angle due to lattice expansion. Overall, the thickness of ${\gamma}_c$ phase showed a linear dependence with respect to increasing temperature due to the faster rate of diffusion of carbon. However, at temperatures above 500, the thickness data deviated from the linear trend. It is expected that the deviation was caused from atomic diffusion as well as other reactions that occurred at high temperatures. The interfacial contact resistance (ICR) and corrosion resistance are measured in a simulated proton exchange membrane fuel cell (PEMFC) environment. The ICR value of the carburized samples decreased from 130 $m{\Omega}cm^2$ (AISI 316L) to about 20 $m{\Omega}cm^2$. The sample carburized at 200 showed the best corrosion current density (6 ${\mu}Acm^{-2}$).

• 한국정보통신학회논문지
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• 제12권10호
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• pp.1890-1896
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• 2008

본 연구는 칩 표면에 수평 한 자기장을 검출하는 종형 Hall 소자를 바이폴라 기술로 제조하여 동작 및 잡음 특성을 조사하였다. P+ Isolation 댐을 설치한 소자(type B)가 설치하지 않는 소자(type A)보다 자기 감도는 약 1.2배 증가하였고, 역시 잡음도 증가하였다. 측정된 이 종형 Hall소자의 자기 검출 분해능은 f=1[KHz], 대역폭 1[Hz] 구동조건에서 type A는 약 $0.97[{\mu}T]$, type B는 $1.25[{\mu}T]$였다. 따라서 Hall 소자 구조 설계나 재료적인 면에서 볼 때, 낮은 잡음즉, 자기 검출분해능과 높은 감도 상관관계를 고려하여야 한다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.1710-1716
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• 2008

The Loop Heat Pipe (LHP) operates to pump the working fluid by means of the capillary force in a wick structure. Particularly, it is difficult to design and manufacture the evaporator consisted of a grooved container and a compensation chamber as well as the wick structure. This study is related to design and manufacture the grooved container coupled with wick structure, the properties of the wick structure such as the permeability, the porosity, and the maximum capillary pressure were measured to apply the cooling technology for Insulated Gate Bipolar Transistor (IGBT). The container of the LHP was manufactured by the electrical discharge process and the wick structure was sintered with the nickel particle by an axial-press apparatus with the pulse electronic discharge. As results, the properties of the wick were experimentally obtained about 60% of the porosity, 35kPa of the maximum capillary force and $1.53{\times}10-13m2$ of the permeability.

• 전기전자학회논문지
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• 제11권4호
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• pp.158-164
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• 2007

본 논문에서는 전력용 스위칭 소자로 널리 활용되고 있는 IGBT 소자 중 수평 게이트 구조보다 우수한 특성을 지닌 트렌치 게이트 IGBT(TIGBT) 구조를 채택하여, 기존의 TIGBT가 갖는 구조적 한계를 극복하고 좀 더 우수한 전기적 특성을 갖는 새로운 구조의 수직형 TIGBT를 제안하였다. 첫 번째로 제안한 IGBT 소자는 P+컬렉터를 산화막으로 고립시킴으로서 N-드리프트 층으로의 정공 주입효율을 극대화하여 기존 구조보다 더 낮은 순방향 전압강하를 얻도록 설계된 구조이다. 두 번째 제안한 구조는 양 게이트 사이의 P-베이스 구조를 볼록하게 형성함으로서 게이트 쪽으로 집중되는 전계의 일부를 접합부 쪽으로 유도하여 기존 구조보다 더 높은 항복전압을 얻을 수 있다. 또한 P-베이스의 볼록한 구조가 턴-오프 시 정공의 흐름을 개선시켜 기존 구조보다 더 빠른 턴-오프 시간을 갖게 된다. 시뮬레이션 결과 첫 번째 구조의 특징은 2.4V의 순방향 전압강하 특성을 갖는 기존의 IGBT 구조보다 상당히 낮은 2.1V의 순방향 전압강하 특성을 나타냈으며, 두 번째 구조는 기존의 IGBT 보다 10V정도 높아진 항복전압 특성을 보였다. 또한 두 번째 구조에서 기존 구조와 비교해볼 때 9ns 정도 빠른 턴-오프 시간을 보였다. 최종적으로 제안된 새로운 구조의 TIGBT는 위 두 구조가 갖는 우수한 전기적 특성을 모두 갖도록 결합한 것이며, 시뮬레이션 결과 기본의 TIGBT 소자보다 순방향 전압강하, 항복특성, 그리고 턴 오프 특성이 모두 우수한 결과를 나타냈다.

• 한국진공학회지
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• 제12권4호
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• pp.239-250
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• 2003

실리콘-게르마늄 이종접합 바이폴라 트랜지스터 (SiGe HBT)에서 발생하는 신뢰성 열화 현상을 고찰하였다. SiGe HBT의 경우에 전류이득 감소, AC특성 저하, 오프셋 전압이 자주 관찰되는데 그 원인으로는 각각 에미터-베이스 역 바이어스 전압 스트레스, 과도촉진확산 (transient enhanced diffusion), 공정 변동 (fluctuation)에 따른 베이스-콜렉터 접합 특성 저하를 들 수 있다. 에미터-베이스 접합에 역 바이어스 전압 스트레스가 걸리면 에미터-베이스 접합면의 테두리 부분에서 높은 에너지를 가지는 전자와 정공들이 생성되고, 이들 전자와 정공들이 실리콘-산화막 계면 및 산화막 내부에 전하를 띈 트랩을 생성하기 때문에 재결합에 의한 베이스 누설전류가 증가하여 소자의 전류이득은 크게 감소하게 된다. 에미터-베이스 접합과 외부 베이스의 거리가 임계 값보다 짧을 때에는 소자의 차단주파수($f_t$)가 감소하게 되는데 이것은 외부 베이스 이온주입에 의하여 내부 베이스 내의 도펀트의 확산이 촉진되어 나타나는 현상이다. 외부 베이스 이온주입 에너지가 충분하지 않은 경우에는 콜렉터-베이스 접합의 턴온 전압이 감소하여 전류-전압 특성 곡선에서 오프셋 전압이 발생하게 된다.