• Title/Summary/Keyword: bipolar junction transistor

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The Design of BCM based Power Factor Correction Control IC for LED Applications (LED 응용을 위한 BCM 방식의 Power Factor Correction Control IC 설계)

  • Kim, Ji-Man;Jung, Jin-Woo;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.6
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    • pp.2707-2712
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    • 2011
  • In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

A Real Time Model of Dynamic Thermal Response for 120kW IGBT Inverter (120kW급 IGBT 인버터의 열 응답 특성 실시간 모델)

  • Im, Seokyeon;Cha, Gangil;Yu, Sangseok
    • Transactions of the Korean hydrogen and new energy society
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    • v.26 no.2
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    • pp.184-191
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    • 2015
  • As the power electronics system increases the frequency, the power loss and thermal management are paid more attention. This research presents a real time model of dissipation power with junction temperature response for 120kw IGBT inverter which is applied to the thermal management of high power IGBT inverter. Since the computational time is critical for real time simulation, look-up tables of IGBT module characteristic curve are implemented. The power loss from IGBT provides a clue to calculate the temperature of each module of IGBT. In this study, temperature of each layer in IGBT is predicted by lumped capacitance analysis of layers with convective heat transfer. The power loss and temperature of layers in IGBT is then communicated due to mutual dependence. In the dynamic model, PWM pulses are employed to calculation real time IGBT and diode power loss. Under Matlab/Simulink$^{(R)}$ environment, the dynamic model is validated with experiment. Results showed that the dynamic response of power loss is closely coupled with effective thermal management. The convective heat transfer is enough to achieve proper thermal management under guideline temperature.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

  • Wang, Yang;Jin, Xiangliang;Zhou, Acheng;Yang, Liu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.601-607
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    • 2015
  • A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

Current Gain Enhancement in SiGe HBTs (SiGe HBT의 Current Gain특성 향상)

  • 송오성;이상돈;김득중
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.5 no.4
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    • pp.367-370
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    • 2004
  • We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

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A SPICE-Compatible Model for a Gate/Body-Tied PMOSFET Photodetector With an Overlapping Control Gate

  • Jo, Sung-Hyun;Bae, Myunghan;Choi, Byoung-Soo;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.24 no.5
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    • pp.353-357
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    • 2015
  • A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

Radiation Damage of Semiconductor Device by X-ray (엑스선에 의한 반도체 소자의 방사선 손상)

  • Kim, D.S.;Hong, H.S.;Park, H.M.;Kim, J.H.;Joo, K.S.
    • Journal of Radiation Protection and Research
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    • v.40 no.2
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    • pp.110-117
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    • 2015
  • Recently, Due to the increased industry using radiation inspection equipment in the semiconductor, this demand of technology research is increasing. Although semiconductor inspection equipment is using low energy X-ray from 40 keV to 120 keV, Studies of radiation damage about the low energy X-ray are lacking circumstance in our country. Therefore, It is study that BJT (bipolar junction transistor) of one type of semiconductor elements are received radiation damage by low energy X-ray. BJT were used to the NXP semiconductor company's BC817-25 (NPN type), and Used the X-ray generator for the irradiation. Radiation damage of BJT was evaluated that confirm to analyse change of collector-emitter voltage of before and after X-ray irradiation when current gain fixed to 10. X-ray generator of tube voltage was setting 40 kVp, 60 kVp, 80 kVp, 100 kVp, 120 kVp and irradiation time was setting 180s, 360s, 540s into 180s intervals. As the result, We confirmed radiation damage in BJT by low energy X-ray under 120 keV energy, and Especially the biggest radiation damage was appeared at the 80 kVp. It is expected that ELDRS (enhanced low dose rate sensitivity) phenomenon occurs on the basis of 80 kVp. This studies expect to contribute effective dose administration of semiconductor inspection equipment using low energy X-ray, Also Research and Development of X-ray filter.

The Study on Highly Miniaturized Active 90°C Phase Difference Power Divider and Combiner for Application to Wireless Communication (무선 통신 시스템 응용을 위한 초소형화된 능동형 90°C 위상차 전력 분배기와 결합기에 관한 연구)

  • Park, Young-Bae;Kang, Suk-Youb;Yun, Young
    • Journal of Advanced Marine Engineering and Technology
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    • v.33 no.1
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    • pp.144-152
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    • 2009
  • This paper propose highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner for application to wireless communication system. The conventional passive $90^{\circ}C$ power divider and combiner cannot be integrated on MMIC because of their very large circuit size. Therefore, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner are required for a development of highly integrated MMIC. In this paper, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner employing InGaAs/GaAs HBT were designed, fabricated on GaAs substrate. According to the results, the circuit size of fabricated active $90^{\circ}C$ phase difference power divider and combiner were $1.67{\times}0.87$ mm and $2.42{\times}1.05$ mm, respectively, which were 31.6% and 2.2% of the size of conventional passive branch-line coupler. The output gain division characteristic of proposed divider circuit showed 8.4 dB and 7.9 dB respectively, and output phase difference characteristic showed $-89.3^{\circ}C$. The output gain coupling characteristic of proposed combiner circuit showed 9.4 dB and 10.5 dB respectively, and output phase difference characteristic showed $-92.6^{\circ}C$. The highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner exhibited good RF performances compared with the conventional passive branch-line coupler.

Design of Ku-Band BiCMOS Low Noise Amplifier (Ku-대역 BiCMOS 저잡음 증폭기 설계)

  • Chang, Dong-Pil;Yom, In-Bok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.199-207
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    • 2011
  • A Ku-band low noise amplifier has been designed and fabricated by using 0.25 um SiGe BiCMOS process. The developed Ku-band LNA RFIC which has been designed with hetero-junction bipolar transistor(HBT) in the BiCMOS process have noise figure about 2.0 dB and linear gain over 19 dB in the frequency range from 9 GHz to 14 GHz. Optimization technique for p-tap value and electro-magnetic(EM) simulation technique had been used to overcome the inaccuracy in the PDK provided from the foundry service company and to supply the insufficient inductor library. The finally fabricated low noise amplifier of two fabrication runs has been implemented with the size of $0.65\;mm{\times}0.55\;mm$. The pure amplifier circuit layout with the reduced size of $0.4\;mm{\times}0.4\;mm$ without the input and output RF pads and DC bais pads has been incorporated as low noise amplication stages in the multi-function RFIC for the active phased array antenna of Ku-band satellite VSAT.

A BJT Structure with High-Matching Property Fabricated Using CMOS Technology (CMOS 기술을 기반으로 제작된 정합 특성이 우수한 BJT 구조)

  • Jung, Yi-Jung;Kwon, Hyuk-Min;Kwon, Sung-Kyu;Jang, Jae-Hyung;Kwak, Ho-Young;Lee, Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.5
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    • pp.16-21
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    • 2012
  • For CMOS based bipolar junction transistor (BJT), a novel BJT structure which has higher matching property than conventional BJT structure was proposed and analyzed. The proposed structure shows a slight decrease of collector current density, $J_C$ about 0.361% and an increase of current gain, ${\beta}$ about 0.166% compared with the conventional structure. However, the proposed structure shows a decrease of area about 10% the improvement of matching characteristics of collector current ($A_{IC}$) and current gain ($A_{\beta}$) about 45.74% and 38.73% respectively. The improved matching characteristic of proposed structure is believed to be mainly due to the decreased distance between two emitters of pair BJTs, which results in the decreased effect of deep n-well of which resistance has the higher standard deviation than the other resistances.