• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.193-199
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• 2009

Powerline communications (PLC) technology has been discussed and analyzed as a highly potential candidate of wireline access network solutions. In this paper, performance of double binary turbo coded orthogonal frequency division multiplexing (OFDM) system is analyzed and simulated in power line communications channel. In order to make power line channel environments, Bernoulli-Gaussian noise is considered. The performance is evaluated in terms of bit error probability. From the simulation results, it is demonstrated that the double binary turbo coding scheme offers considerable coding gain with reasonable encoding complexity. It is also shown that the system performance can be substantially improved by increasing the number of iterations.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.959-962
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• 2005

Recently, business integration and interoperability of between the heterogeneous applications are requested by rapid growth of web. Web Services that self-contained for platform and programming language is appeared used to XML of standard data format. Such amid Fast Web Services attract attention at fields necessary to bring rapid communication like Mobile and RFID. In this paper, we inquired about ASN.1 of ITU-T and IS0/IEC standard that a central role of data transform. And we studied encoding process of between ASN.1 and XML for transform SOAP massage of a massage transfer mode of Web Services to binary data.

• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.94-104
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• 1997

This paper presents a new vertex-based binary shape coding scheme using one-dimensional vertex selection/encoding and vertex reordering. In compared with the conventional object-adaptive vertex encoding(OA VEL the extracted vertices are, firstly, classified into one-dimensional(lD) vertices and two-dimensional (2D) vertices in the proposed method. For lD vertices, new coding method proposed in this paper is performed. For 2D vertices, the vertex reordering and OA VE are carried out. Experimental results show that the proposed vertex-based coding scheme red.uces coding bits up to 12 % compared with the conventional one and its coding gain depends on the characteristics of contour.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.77-84
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• 2013

In this paper, we review two-dimensional measuring methods referring to target patterns. The patterns consist of two linearly-repeated patterns or is designed repeatedly in two-dimension. The repeated properties are reflectivity, refractivity, air-gapping distance, capacitance, magnetic reluctance, electrical resistance and sloping gradient, etc. However, the optical methods are generally used for high speed processing and density, and their encoding principles are treated here. In case of two-dimensional pattern, as there is not inherently error between single units encoding the pattern except for the metrology frame errors, the end-effector position of an object accompanying the pattern can be measured with respect of the global frame without via error. Therefore, it is regarded as a substitute for laser interferometer with severe environmental constraints and has been applied to the high-accurate planar actuator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2C
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• pp.100-109
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• 2003

A differential index assignment scheme is proposed for the image encoding system in which a variable-length tree-structured vector quantizer is adopted. Each source vector is quantized into a terminal node of VLTSVQ and each terminal node is represented as a unique binary vector. The proposed index assignment scheme utilizes the correlation between interblocks of the image to increase the compression ratio with the image quality maintained. Simulation results show that the proposed scheme achieves a much higher compression ratio than the conventional one does and that the amount of the bit rate reduction of the proposed scheme becomes large as the correlation of the image becomes large. The proposed encoding scheme can be effectively used to encode R images whose pixel values we, in general, highly correlated with those of the neighbor pixels.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.3286-3300
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• 2016

High Efficiency Video Coding (HEVC) Standard, as the latest coding standard, introduces satisfying compression structures with respect to its predecessor Advanced Video Coding (H.264/AVC). The new coding standard can offer improved encoding performance compared with H.264/AVC. However, it also leads to enormous computational complexity that makes it considerably difficult to be implemented in real time application. In this paper, based on machine learning, a fast partitioning method is proposed, which can search for the best splitting structures for Intra-Prediction. In view of the video texture characteristics, we choose the entropy of Gray-Scale Difference Statistics (GDS) and the minimum of Sum of Absolute Transformed Difference (SATD) as two important features, which can make a balance between the computation complexity and classification performance. According to the selected features, adaptive decision trees can be built for the Coding Units (CU) with different size by offline training. Furthermore, by this way, the partition of CUs can be resolved as a binary classification problem. Experimental results have shown that the proposed algorithm can save over 34% encoding time on average, with a negligible Bjontegaard Delta (BD)-rate increase.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.810-820
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• 2001

Conventional binary adder requires a carry propagation to the most significant bit, and leads to serial addition. However, optical adder using a modified signed digit(MSD) number system has been Proposed to reduce the carry propagation chain encountered in binary adder. In this paper, in order to minimize the number of symbolic substitution(SS) rules, nine input patterns were divided into five groups of the same addition results. For recognizing the input reference patterns, serial connections of joint spatial encoded patterns and masks without any other spatial operations are used.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.