• Title/Summary/Keyword: binary arithmetic coding

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Multi-Symbol Binary Arithmetic Coding Algorithm for Improving Throughput in Hardware Implementation

  • Kim, Jin-Sung;Kim, Eung Sup;Lee, Kyujoong
    • Journal of Multimedia Information System
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    • v.5 no.4
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    • pp.273-276
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    • 2018
  • In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

The Hardware Design of CABAC for High Performance H.264 Encoder (고성능 H.264 인코더를 위한 CABAC 하드웨어 설계)

  • Myoung, Je-Jin;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.771-777
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    • 2012
  • This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

Performance Improvement of Binary MQ Arithmetic Coder (2진 MQ 산술부호기의 성능 개선)

  • Ko, Hyung Hwa;Seo, Seok Yong
    • Journal of Advanced Navigation Technology
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    • v.19 no.6
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    • pp.614-622
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    • 2015
  • Binary MQ arithmetic coding is widely used recently as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as an unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity happened in MQ coder, output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of a lookup table for AQe using quantization skill in order to reduce the deficiency. Experimental results show that about 4% improvement of compression in case of JBIG2 for bi-level image compression standard. And also, about 1% improvement of compression ratio is obtained in case of lossless JPEG2000 coding. For the lossy JPEG2000 coding, about 1% improvement of PSNR at the same compression ratio. Additionally, computational complexity is not increasing.

Design of a Pipelined Binary Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 파이프라인 이진 산술 부호화기 설계)

  • Yun, Jae-Bok;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.42-49
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    • 2007
  • CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

Design of an Efficient Binary Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 효율적인 이진 산술 부호화기 설계)

  • Moon, Jeon-Hak;Kim, Yoon-Sup;Lee, Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.66-72
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    • 2009
  • This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

Improved CABAC Method for Lossless Image Compression (무손실 영상 압축을 위한 향상된 CABAC 방법)

  • Heo, Jin;Ho, Yo-Sung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.6C
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    • pp.355-360
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    • 2011
  • In this paper, we propose a new context-based adaptive binary arithmetic coding (CABAC) method for lossless image compression. Since the conventional CABAC in H.264/AVC was originally designed for lossy coding, it does not yield adequate performance during lossless coding. Therefore, we proposed an improved CABAC method for lossless intra coding by considering the statistical characteristics of residual data in lossless intra coding. Experimental results showed that the proposed method reduced the bit rate by 18.2%, compared to the conventional CABAC for lossless intra coding.

Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder

  • Pham, Duyen Hai;Moon, Jeonhak;Kim, Doohwan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.630-635
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    • 2014
  • In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

Design of High Speed Binary Arithmetic Encoder for CABAC Encoder (CABAC 부호화기를 위한 고속 이진 산술 부호화기의 설계)

  • Park, Seungyong;Jo, Hyungu;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.4
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    • pp.774-780
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    • 2017
  • This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

A DATA COMPRESSION METHOD USING ADAPTIVE BINARY ARITHMETIC CODING AND FUZZY LOGIC

  • Jou, Jer-Min;Chen, Pei-Yin
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1998.06a
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    • pp.756-761
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    • 1998
  • This paper describes an in-line lossless data compression method using adaptive binary arithmetic coding. To achieve better compression efficiency , we employ an adaptive fuzzy -tuning modeler, which uses fuzzy inference to deal with the problem of conditional probability estimation. The design is simple, fast and suitable for VLSI implementation because we adopt the table -look-up approach. As compared with the out-comes of other lossless coding schemes, our results are good and satisfactory for various types of source data.

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A Study on the Hardware Design of High-Throughput HEVC CABAC Binary Arithmetic Encoder (높은 처리량을 갖는 HEVC CABAC 이진 산술 부호화기의 하드웨어 설계에 관한 연구)

  • Jo, Hyun-gu;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.401-404
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    • 2016
  • This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

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