• Journal of the Korean Operations Research and Management Science Society
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• v.24 no.2
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• pp.81-94
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• 1999

ATM network design procedure is different from the current circuit or packet networks design procedure because of the variety of the offered services and the variability of requested bandwidth for each connection of ATM network. A number of optimization models for the link dimensioning of ATM network design have been proposed in the literature. However, most of the literature did not consider the modularity of resources allocated to a transmission path and the non-bifurcation of a VP link over the more than one TP, which are standardized in recent ITU-T Recommendations. In thIs paper, we propose a mathematical model for link dimensioning of ATM networks, based on the network synthesis method and a generalized bin-packing problem. The suggested model satisfies the constraints mentioned in the ITU-T Recommendations. We also propose efficient and practical algorithms for the suggested model. Computational experiment shows that the suggested algorithm gives efficient solutions even for moderate and large-sized networks within reasonable time.

• Management Science and Financial Engineering
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• v.11 no.2
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• pp.61-84
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• 2005

This paper considers a special case of the two-dimensional bin-packing problem for identical items. The objective of this work is to maximize the space utilization. The main contribution of the paper is to suggest a new heuristic algorithm keeping in view the existing complexity of racking system for the footwear boxes in the compartments of different sizes for a warehouse. The results show that a significant improvement can be obtained. An economic choice of compartments is also estimated using the criteria for maximizing space utilization. A non-linear mathematical model was presented based on the constraints of racking dynamics.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.137-142
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• 2006

제철소 후판공장에서는 두꺼운 슬라브(Slab)를 압연하여 사각형태의 철판인 날판(Mother Plate)을 생산하고, 이를 주문(Plate) 사이즈에 맞게 다시 절단을 하게 된다. 이때 동일 슬라브라 하더라도 압연방법에 따라 다양한 사이즈의 날판을 생산할 수 있다. 여기에서 다루고 있는 후판 날판설계 문제는 주어진 주문을 대상으로 최소 개수의 슬라브를 사용하여 생산하는 문제를 말한다. 이를 위해 최적의 날판 사이즈를 결정하고, 각 날판에 주문들을 배치하게 된다. 본 논문에서는 후판 날판설계문제를 two-stage guillotine cutting problem의 변이로 모델을 세우고, 이를 위한 효율적인 휴리스틱을 제시하였다. 그리고 실 데이터를 대상으로 컴퓨터 실험을 통해 휴리스틱을 효율성을 검정하였다.

• Management Science and Financial Engineering
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• v.18 no.1
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• pp.39-48
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• 2012

This article presents a way of tackling a special class of space optimization problems that arise in a number of practical applications in industry and elsewhere. It presents an elegant solution to a problem that was considered by (Das, 2005) in optimizing storage space in warehouse of a footwear manufacturing company. In (Das, 2005), the problem was formulated as a nonlinear programming problem. In this article, it is shown that the problem can be formulated as a generalized transportation problem which is a special case of generalized network flow problems. Further, an elegant scheme is devised to handle the dynamic situation of warehousing problem which can be easily translated into a decision support system for the warehouse management system. Also, the article points out certain obscurities and gaps in (Das, 2005).

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.545-551
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• 2013

Packed technique makes difficult to respond quickly because the malicious-code is reduced size that easy to diffusion and changed code that make spend longer time for analysis. In this paper, we analysed the packing tool softwares and we proposed construction and detection methods of the packed technique for easy to analysis of the packed malicious code based on variation of entropy value.

• Journal of Biosystems Engineering
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• v.34 no.5
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• pp.342-350
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• 2009

Currently TMR feed produced in commercial plant is one of the major source to feed cattle for both beef and dairy farm. However, because of lack of cutting and mixing system for utilizing domestic produced firmly baled round roughage in commercial TMR plant, these commercial TMR feed can not satisfy to farmers both in quality and price points of view. In order to solve these problems, a farm group size TMR plant model was developed in this study. The model plant was consist of round bale receiving and cutting system, pneumatic conveying system for transfer the roughage which was cut at the cutter to TMR mixer through pneumatic conveyor, TMR mixer enable to soften the stiff rice strew and to mix with other ingredients, finished feed bin which can be transfer to either packing system or individual farm, packing system by tycon bag which contains 400 kg unit and bulk unloading system to individual farmer. Also, a simulation model ARENA was applied to the model system in order to evaluate and check the production rate in each unit process and operation rate of total system and to find out if there are any clogged unit system obstructing the smooth flow of the total process flow. Processing cycle for produce one batch of the model plant was less than 30 minutes. Thus, it will take less than four hours for producing 16 tons per day equivalent to 1,000 beef cattle's daily feed.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1993.10a
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• pp.12-19
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• 1993

In general, the line balancing problem is defined as of finding an assignment of the given jobs to the workstations under the precedence constraints given to the set of jobs. Usually, the objective is either minimizing the cycle time under the given number of workstations or minimizing the number of workstations under the given cycle time. In this paper, we present a new type of an assembly line balancing problem which occurs in an electronics company manufacturing home appliances. The main difference of the problem compared to the general line balancing problem lies in the structure of the precedence given to the set of jobs. In the problem, the set of jobs is partitioned into two disjoint subjects. One is called the set of fixed jobs and the other, the set of floating jobs. The fixed jobs should be processed in the linear order and some pair of the jobs should not be assigned to the same workstations. Whereas, to each floating job, a set of ranges is given. The range is given in terms of two fixed jobs and it means that the floating job can be processed after the first job is processed and before the second job is processed. There can be more than one range associated to a floating job. We present a procedure to find an approximate solution to the problem. The procedure consists of two major parts. One is to find the assignment of the floating jobs under the given (feasible) assignment of the fixed jobs. The problem can be viewed as a constrained bin packing problem. The other is to find the assignment of the whole jobs under the given linear precedence on the set of the floating jobs. First problem is NP-hard and we devise a heuristic procedure to the problem based on the transportation problem and matching problem. The second problem can be solved in polynomial time by the shortest path method. The algorithm works in iterative manner. One step is composed of two phases. In the first phase, we solve the constrained bin packing problem. In the second phase, the shortest path problem is solved using the phase 1 result. The result of the phase 2 is used as an input to the phase 1 problem at the next step. We test the proposed algorithm on the set of real data found in the washing machine assembly line.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.