• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• Journal of the Korean Society of School Health
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• v.29 no.3
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• pp.123-131
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• 2016

Purpose: Human Papillomavirus(HPV) vaccination is the best prevention for cervical cancer. Therefore, this study was to examine the best predictors of HPV vaccination status in female nursing university students. Methods: Five hundred and forty junior and senior female nursing students from Seoul and provinces of Kyunggi, Chungcheong and Gyungsang completed paper and pencil questionnaires. Descriptive statistics, $x^2$ test, t-test, and multiple logistic regression with dummy variables were conducted using SAS 9.2. Results: Of the total students, 56.8% were vaccinated. As a result of the analysis of the bivariate relationships, family economic status, school type, perceived susceptibility, perceived benefit and perceived barriers (cost, time, distance from hospital and side effects) were significantly related to vaccination status. After controlling for the general characteristics and the HPV related knowledge score, higher family economic status (Adjusted Odds Ratio [AOR]: 3.78, 95% Confidence Interval [CI]: 1.21~11.76), private university (AOR: 1.69, 95% CI: 1.14~2.53), higher perceived benefit (AOR: 1.80, 95% CI: 1.47~2.20), lower perceived barrier (cost) (AOR: 0.86, 95% CI: 0.74~0.99), lower perceived barrier (time) (AOR: 0.71, 95% CI: 0.61~0.84), and lower perceived barrier (side effects) (AOR: 0.82, 95% CI: 0.72~0.94) were significantly related to HPV vaccination. Perceived benefit, perceived barrier (time) and perceived barrier (side effects) were the top 3 predictors of HPV vaccination status. Conclusion: This study suggests that vaccinated female nursing students were more likely to be from higher family economic status and private universities and have a higher perception of benefit and a lower perception of barriers (cost, time, and side effects). Thus, efforts to increase HPV vaccination rates of female nursing students should focus on improving their perception of benefit while lowering their perception of barriers, particularly cost, time and side effects.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1646-1649
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• 2012

The $O_2$ annealing technique has considerably suppressed the leakage current of GaN power devices, but this forms NiO at Ni-based Schottky contact with increasing on-resistance. The purpose of the present study was to fabricate 1.5 kV GaN Schottky barrier diodes by improving $O_2$-annealing process and GaN buffer. The proposed $O_2$ annealing performed after alloying ohmic contacts in order to avoid NiO construction. The ohmic contact resistance ($R_C$) was degraded from 0.43 to $3.42{\Omega}-mm$ after $O_2$ annealing at $800^{\circ}C$. We can decrease RC by lowering temperature of $O_2$ annealing. The isolation resistance of test structure which indicated the surface and buffer leakage current was significantly increased from $2.43{\times}10^7$ to $1.32{\times}10^{13}{\Omega}$ due to $O_2$ annealing. The improvement of isolation resistance can be caused by formation of group-III oxides on the surface. The leakage current of GaN Schottky barrier diode was also suppressed from $2.38{\times}10^{-5}$ to $1.68{\times}10^{-7}$ A/mm at -100 V by $O_2$ annealing. The GaN Schottky barrier diodes achieved the high breakdown voltage of 700, 1400, and 1530 V at the anode-cathode distance of 5, 10, and $20{\mu}m$, respectively. The optimized $O_2$ annealing and $4{\mu}m$-thick C-doped GaN buffer obtained the high breakdown voltage at short drift length. The proposed $O_2$ annealing is suitable for next-generation GaN power switches due to the simple process and the low the leakage current.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.683-685
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• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2015-2020
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• 2012

The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.